Block RAM in Xilinx FPGAs

[xtcx]

In one of my projects using FPGA,I have got over 98% occupation of logic gates. Lines and lines of program.I never used block ram. In my program I have lots of arrays. So i tried using block ram and configured as "read only". So I was able to store some data's in the ROM at some addr location using the memory editor in Core generator tools provided with Xilinx ISE 8.2i. I was able to read data in the program very well now, but te resulting logic gates constraints was now only 97%.I removed about 7 arrays of 8-bit datas with depth of 16.My program is about 1800 lines.Perhaps it smashed my expectations.No impovement.Later when I reduce some 200 lines of some IF-Else statements in the program, the ratio drops to some 35%.Amazing yet surprising.So why removing arrays by using RAM won't cut down the constraints ratio?....
My Xilinx version is 7.1i (also tried on 8.2i)
FPGA - SPARTAN 3(400K).
I used Block RAM IPCORE program.Please provide some help here ....Any reason why block ram is not reducing my gates package size?.:?:

 

[zeeshanzia84]

Are you sure Block RAM is actually being sythesized? Does it show up while synthesizing (or in the synthesis report)?

 

[it_boy]

one possibility is that you might have used Distributed RAM for your arrays. ISE targets distributed RAM depending on the way you code. I think Spartan-3 can store 16-bits of data in one LUT. So, your 7 arrays of 8-bit data might have consumed only 8 LUTs. So, when you targetted BRAMs, you did not save much

 

[ydragon]

In my opnion, the result is ok.
first, too many if else will consume much slices resource,
second, the LUT can be configured as distribute ram, and this transformation is effective, your 8x16 RAM can be implimented as LUT. and 7 array only consume several LUT, that's why the ratio don't change much

 

[kingbeful]

You should write the HDL code this
initial

$readmemb("blk_mem_ram.mif", mem, 8'h00, 8'hff);



always @ (posedge clk) begin

if (mem_rd_en) begin

mem_data_out <= mem[mem_addr_out];

end

if (mem_wr_en) begin

mem[mem_addr_in] <= mem_data_in;

end

end

and ISE will know that what you want is a block ram, otherwise, your designe will be synthesized into distrbute ram. And it may use all of your logic gates

 

[xtcx]

Thanks for your replies...First I need to say that I used Xilinx's IP core generator tool that came with ISE 8.2i pack. I selected Block ram IP and chose read-write mode and entered the width and depth and then generated that ram-file. After this,I added this file to the structural part as component of my top-module.From my program I used the addr and data in and data out ports of xilinx generated IP to store or retrieve the data. I didn't use any syntax in my program for Block-ram. So I guess, I wasn't using Distributed RAM for sure. Also the program works as usual. But ideally moving the array data to RAM didn't do any help...But for some of my friends,they have reduced their constraints ratio to some better by using block-ram for their project.My downside is that I used too many say over some 40 to 50 flags for checking and many IF-ELSE stats. Could this be a prob?. Also using package or functions might help reducing gates usage?.Please help