Bitwise AND operation between different width vector

[yuenkit]

module fsm1 (x, clk, rst, y);
input x, clk, rst;
output y;
parameter [3:0]
set0 = 4'b0001, hold0 = 4'b0010, set1 = 4'b0100, hold1 = 4'b1000;
reg [3:0] current_state, next_state;

always @ (posedge clk or posedge rst)
  if (rst)
    current_state = set0;
  else
  current_state = next_state;

always @ (current_state or x)
  case (current_state)
  set0:
    next_state = hold0;
  hold0:
    if (x == 0)
      next_state = hold0;
  else
    next_state = set1;
  set1:
    next_state = hold1;
  hold1:
    next_state = set0;
  default :
    next_state = set0;
  endcase
  
  assign y = current_state == hold0 & x;
  endmodule

Please look at the last line :
assign y = current_state == hold0 & x;

hold0 is a 4 bit variable with the value 4'b0010, and x is a single bit variable.
when they ANDed together, will it posible to get a TRUE value?

I thought, x will be zero extended to match the length of hold0, which will be 4'b000x, so no matter what x value is, the result is always false.

The above FSM i taken from the DC Presto compiler manual. It seems like the output will be 1 if the x is 1.

 

[jarodz]

In my memory, the output of (current_state == hold0) is true or false, so it only need a bit.
You can write the code seperately as below,

wire    is_hold0_state = (current_state == hold0);
wire    y = is_hold0_state & x;

Sincerely,
Jarod

 

[yuenkit]

assign y = current_state == hold0 & x;
is basically
assign y = (current_state == hold0) & x;

thanks!

previously i thought
assign y = current_state == (hold0 & x);