Bitstream generation after some change of VHDL code

Status
Not open for further replies.

BlackOps

Full Member level 5
Joined
Jan 1, 2005
Messages
279
Helped
14
Reputation
28
Reaction score
3
Trophy points
1,298
Location
AZERBAIJAN
Activity points
2,496
Hello, i am using EDK 9.1

I have added standard peripheral using wizard. Then for example i want to add some changes to the VHDL code of the peripheral.. but if i want to generate bitstream again, it takes again a lot of time...even after some little change in VHDL...

is there a way of not generating the whole VHDL code....but rather to re-generate the part which changed? i hope u understand me... cuz it takes lot of time

thanks
 

You can't help it buddy. Even a single line of code change (in a single file!) required re-run of synthesis, implementation(translate, map, p&r) & programming file generation steps all over again.

You can upgrade your workstation's processor or increase the RAM. This might finish the activities faster :|
 

Status
Not open for further replies.

Similar threads

Menu
Log in
Register
Cookies are required to use this site. You must accept them to continue using the site. Learn more…