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yep. as mentioned last time, the config (virtex-5) and partial reconfig guides (ISE12 documentation). the partial reconfig guides (ise12) guide mentions "frames" as well as documents some of the dynamic reconfiguration issues.
If you know how the bitstream is working you now the full structure/layout of the fpga, xilinx/altera is not giving you this details because then they have opened everything to other FPGA vendors.
Virtex-5 configuration guide explains the configuration memory addressing and how it corresponds to the FPGA layout, but of course it doesn't explain the internal correspondence between bitstream and logic blocks.
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