[SOLVED] Bit swapping in Verilog

[andre_luis]

A time ago I came across a piece of code intended to perform a bit reversing operation ( swapping the most significant bits toward less significant bits, and vice-versa ), but it seemed that would not work, like if one would superimpose the value of the other. Is it correct ?

for(i=0;i<8;i=i+1)
   begin 
      a_temp<=a[7-i];
      a[7-i]<=a[i];
      a[i]<=a_temp;      
   end
end

 

[FvM]

Re: reverse bits in verilog

The original code works. By using nonblocking assignments, the left-hand side of expressions is updated after the end of the initial block.

 

[andre_luis]

Re: reverse bits in verilog

Thanks for correcting me, so can we assume that the code below will perform the same bit swapping task, but coded in a simplest manner ?

a[0:7] <= a[7:0] ;

 

[dave_59]

Re: reverse bits in verilog

Thanks for correcting me, so can we assume that the code below will perform the same bit swapping task, but coded in a simplest manner ?

a[0:7] <= a[7:0] ;

No, that will not work. You cannot have a select of bits in the reverse order.

In SystemVerilog, there is a streaming operator that will reverse the bits for you.

a <= {<<{ a }};

See section 11.4.14 Streaming operators (pack/unpack) in the IEEE 1800-2012 LRM.