[SOLVED] bit-select or part-select is not allowed in a assign statement for non-net

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stackprogramer

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How can I initialize a reg array in Verilog...Any offer?
Code: 
reg m_shift_value[3:0];
    initial begin   
          //Initial registers
          assign {m_shift_value[3],m_shift_value[2],m_shift_value[1],m_shift_value[0]} = {0, 32, 64, 96};
      end
 

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Why are you using assign statement in an initial block where you should use = ?
How are assigning decimal literals to a bit array that can only take 0 and 1 values?
 
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Thanks very much so I concluded that I should use this method for initializing the reg array...
I should use assign for wires...
Code: 
initial
          begin
              reg m=0;
            for (k = 0; k < 4 - 1; k = k + 1)
              begin
                  m_shift_value[k] = m;
                  m=m+32;
              end
          end
 

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