[B]read_verilog b04_gate.v[/B]
Error: File: b04_gate.v, Line: 55: Bit-select of undeclared variable 'DATA_IN' used in module 'b04'.
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 LIBRARY IEEE; USE IEEE.std_logic_1164.all; USE IEEE.std_logic_arith.all; entity b04 is port( RESTART : in bit; AVERAGE : in bit; ENABLE : in bit; DATA_IN : in integer range 127 downto -128; DATA_OUT : out integer range 127 downto -128; RESET : in bit; CLOCK : in bit ); end b04; architecture BEHAV of b04 is constant sA : integer := 0; constant sB : integer := 1; constant sC : integer := 2; begin process(CLOCK,RESET) variable stato : integer range 2 downto 0; variable RMAX, RMIN, RLAST, REG1, REG2, REG3, REG4, REGD : integer range 127 downto -128; variable temp : integer; variable RES, AVE, ENA : bit; begin if RESET = '1' then stato := sA; RMAX := 0; RMIN := 0; RLAST := 0; REG1 := 0; REG2 := 0; REG3 := 0; REG4 := 0; DATA_OUT <= 0; elsif CLOCK'event and CLOCK='1' then RES := RESTART; ENA := ENABLE; AVE := AVERAGE; case stato is when sA => stato := SB; when sB => RMAX := DATA_IN; RMIN := DATA_IN; REG1 := 0; REG2 := 0; REG3 := 0; REG4 := 0; RLAST := 0; DATA_OUT <= 0; stato := sC; when sC => if (ENA = '1') then RLAST := DATA_IN; end if; if (RES = '1') then REGD := (RMAX+RMIN)mod 128; temp := RMAX+RMIN; if (temp >= 0) then DATA_OUT <= REGD/2; else DATA_OUT <= -((-REGD)/2); end if; elsif (ENA = '1') then if (AVE = '1') then DATA_OUT <= REG4; else REGD := (DATA_IN+REG4) mod 128; temp := DATA_IN+REG4; if (temp >= 0) then DATA_OUT <= REGD/2; else DATA_OUT <= -((-REGD)/2); end if; end if; else DATA_OUT <= RLAST; end if; if DATA_IN > RMAX then RMAX := DATA_IN; elsif DATA_IN < RMIN then RMIN := DATA_IN; end if; REG4 := REG3; REG3 := REG2; REG2 := REG1; REG1 := DATA_IN; stato := sC; end case; end if; end process; End BEHAV;
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 module b04 ( RESTART, AVERAGE, ENABLE, .DATA_IN({\DATA_IN[7] , \DATA_IN[6] , \DATA_IN[5] , \DATA_IN[4] , \DATA_IN[3] , \DATA_IN[2] , \DATA_IN[1] , \DATA_IN[0] }), .DATA_OUT({\DATA_OUT[7] , \DATA_OUT[6] , \DATA_OUT[5] , \DATA_OUT[4] , \DATA_OUT[3] , \DATA_OUT[2] , \DATA_OUT[1] , \DATA_OUT[0] }), RESET, CLOCK ); input RESTART, AVERAGE, ENABLE, \DATA_IN[7] , \DATA_IN[6] , \DATA_IN[5] , \DATA_IN[4] , \DATA_IN[3] , \DATA_IN[2] , \DATA_IN[1] , \DATA_IN[0] , RESET, CLOCK; output \DATA_OUT[7] , \DATA_OUT[6] , \DATA_OUT[5] , \DATA_OUT[4] , \DATA_OUT[3] , \DATA_OUT[2] , \DATA_OUT[1] , \DATA_OUT[0] ; wire N16, N17, N18, N19, N20, N39, N40, N42, N50, N77, N79, N82, N83, N84, N85, N86, N87, N100, N101, N102, N103, N104, N105, N117, N118, N119, N120, N121, N122, N123, N124, N141, N142, N143, N144, N145, N146, N147, N148, N165, N167, N169, N170, N171, N172, N173, N174, N175, N176, N177, N178, N179, N180, N181, N182, N183, N184, N185, N186, N187, N188, N189, N190, N191, N192, N193, N194, N195, N196, N197, N198, N199, N200, N201, N202, N203, N204, N205, N206, N207, N208, N209, N210, N211, N212, N213, N214, N215, N216, N217, N218, N219, N220, N221, N222, N223, N224, N225, N226, N227, N228, \U3/U3/Z_0 , \U3/U3/Z_1 , \U3/U3/Z_2 , \U3/U3/Z_3 , \U3/U3/Z_4 , \U3/U3/Z_5 , \U3/U3/Z_6 , \U3/U3/Z_8 , \U3/U4/Z_0 , \U3/U4/Z_1 , \U3/U4/Z_2 , \U3/U4/Z_3 , \U3/U4/Z_4 , \U3/U4/Z_5 , \U3/U4/Z_6 , \U3/U4/Z_8 , \U3/U5/Z_0 , n70, n71, n72, n73, n74, n75, n76, n77, n78, n79, n80, n81, n82, n83, n84, n85, n86, n87, n88, n89, n90, n91, n92, n93, n94, n95, n96, n97, n98, n99, n100, n101, n102, n103, n104, n105, \r34/B_not[7] , \r34/B_not[6] , \r34/B_not[5] , \r34/B_not[4] , \r34/B_not[3] , \r34/B_not[2] , \r34/B_not[1] , \r34/B_not[0] , \r34/carry[7] , \r34/carry[6] , \r34/carry[5] , \r34/carry[4] , \r34/carry[3] , \r34/carry[2] , \r34/carry[1] , \r34/carry[0] , \r176/B_not[6] , \r176/B_not[5] , \r176/B_not[4] , \r176/B_not[3] , \r176/B_not[2] , \r176/B_not[1] , \r176/carry[7] , \r176/carry[6] , \r176/carry[5] , \r176/carry[4] , \r176/carry[3] , \r176/carry[2] , \r176/carry[1] , \r174/carry[8] , \r33/carry[6] , \r33/carry[5] , \r33/carry[4] , \r33/carry[3] , \r33/carry[2] , \r33/carry[1] , n106, n107, n108, n109, n110, n111, n112, n113, n114, n115, n116, n117, n118, n119, n120, n121, n122, n123, n124, n125, n126, n127, n128, n129, n130, n131, n132, n133, n134, n135, n136, n137, n138, n139, n140, n141, n142, n143, n144, n145, n146, n147, n148, n149, n150, n151, n152, n153, n154, n155, n156, n157, n158, n159, n160, n161, n162, n163, n164, n165, n166, n167, n168, n171, n172, n173, n174, n175, n176, n177, n178, n179, n180, n181, n182, n183, n184, n185, n186, n187, n188, n189, n190, n191, n192, n193, n194, n195, n196, n197, n198, n199; wire [1:0] stato; wire [7:0] RMAX; wire [7:0] RMIN; wire [7:0] RLAST; wire [7:0] REG1; wire [7:0] REG2; wire [7:0] REG3; wire [7:0] REG4; AND2D2 C1020 ( .A1(N77), .A2(RLAST[0]), .Z(N228) ); AND2D2 C1019 ( .A1(ENABLE), .A2(DATA_IN[0]), .Z(N227) ); OR2D2 C1018 ( .A1(N227), .A2(N228), .Z(N148) ); AND2D2 C1016 ( .A1(N77), .A2(RLAST[1]), .Z(N226) ); AND2D2 C1015 ( .A1(ENABLE), .A2(DATA_IN[1]), .Z(N225) ); OR2D2 C1014 ( .A1(N225), .A2(N226), .Z(N147) ); AND2D2 C1012 ( .A1(N77), .A2(RLAST[2]), .Z(N224) ); AND2D2 C1011 ( .A1(ENABLE), .A2(DATA_IN[2]), .Z(N223) ); OR2D2 C1010 ( .A1(N223), .A2(N224), .Z(N146) ); AND2D2 C1008 ( .A1(N77), .A2(RLAST[3]), .Z(N222) ); AND2D2 C1007 ( .A1(ENABLE), .A2(DATA_IN[3]), .Z(N221) ); OR2D2 C1006 ( .A1(N221), .A2(N222), .Z(N145) ); AND2D2 C1004 ( .A1(N77), .A2(RLAST[4]), .Z(N220) ); AND2D2 C1003 ( .A1(ENABLE), .A2(DATA_IN[4]), .Z(N219) ); OR2D2 C1002 ( .A1(N219), .A2(N220), .Z(N144) ); AND2D2 C1000 ( .A1(N77), .A2(RLAST[5]), .Z(N218) ); AND2D2 C999 ( .A1(ENABLE), .A2(DATA_IN[5]), .Z(N217) ); OR2D2 C998 ( .A1(N217), .A2(N218), .Z(N143) ); AND2D2 C996 ( .A1(N77), .A2(RLAST[6]), .Z(N216) ); AND2D2 C995 ( .A1(ENABLE), .A2(DATA_IN[6]), .Z(N215) ); OR2D2 C994 ( .A1(N215), .A2(N216), .Z(N142) ); AND2D2 C992 ( .A1(N77), .A2(RLAST[7]), .Z(N214) ); AND2D2 C991 ( .A1(ENABLE), .A2(DATA_IN[7]), .Z(N213) ); OR2D2 C990 ( .A1(N213), .A2(N214), .Z(N141) ); INVD4 I_8 ( .A(AVERAGE), .Z(N79) ); INVD4 I_7 ( .A(ENABLE), .Z(N77) ); INVD4 I_4 ( .A(N19), .Z(N20) ); INVD4 I_3 ( .A(N17), .Z(N18) ); OR2D2 C856 ( .A1(N18), .A2(n113), .Z(N169) ); DFFRPQ1 \stato_reg[0] ( .D(N16), .CK(CLOCK), .RB(n110), .Q(stato[0]) ); DFFRPQ1 \stato_reg[1] ( .D(N169), .CK(CLOCK), .RB(n122), .Q(stato[1]) ); DFERPQ1 \RMAX_reg[0] ( .D(DATA_IN[0]), .CEB(n73), .CK(CLOCK), .RB(n123), .Q(RMAX[0]) ); DFERPQ1 \RMAX_reg[1] ( .D(DATA_IN[1]), .CEB(n73), .CK(CLOCK), .RB(n110), .Q(RMAX[1]) ); DFERPQ1 \RMAX_reg[2] ( .D(DATA_IN[2]), .CEB(n73), .CK(CLOCK), .RB(n123), .Q(RMAX[2]) ); DFERPQ1 \RMAX_reg[3] ( .D(DATA_IN[3]), .CEB(n73), .CK(CLOCK), .RB(n123), .Q(RMAX[3]) ); DFERPQ1 \RMAX_reg[4] ( .D(DATA_IN[4]), .CEB(n73), .CK(CLOCK), .RB(n121), .Q(RMAX[4]) ); DFERPQ1 \RMAX_reg[5] ( .D(DATA_IN[5]), .CEB(n73), .CK(CLOCK), .RB(n111), .Q(RMAX[5]) ); DFERPQ1 \RMAX_reg[6] ( .D(DATA_IN[6]), .CEB(n73), .CK(CLOCK), .RB(n121), .Q(RMAX[6]) ); DFERPQ1 \RMAX_reg[7] ( .D(DATA_IN[7]), .CEB(n73), .CK(CLOCK), .RB(n121), .Q(RMAX[7]) ); DFERPQ1 \RMIN_reg[0] ( .D(DATA_IN[0]), .CEB(n72), .CK(CLOCK), .RB(n122), .Q(RMIN[0]) ); DFERPQ1 \RMIN_reg[1] ( .D(DATA_IN[1]), .CEB(n72), .CK(CLOCK), .RB(n110), .Q(RMIN[1]) ); DFERPQ1 \RMIN_reg[2] ( .D(DATA_IN[2]), .CEB(n72), .CK(CLOCK), .RB(n122), .Q(RMIN[2]) ); DFERPQ1 \RMIN_reg[3] ( .D(DATA_IN[3]), .CEB(n72), .CK(CLOCK), .RB(n122), .Q(RMIN[3]) ); DFERPQ1 \RMIN_reg[4] ( .D(DATA_IN[4]), .CEB(n72), .CK(CLOCK), .RB(n124), .Q(RMIN[4]) ); DFERPQ1 \RMIN_reg[5] ( .D(DATA_IN[5]), .CEB(n72), .CK(CLOCK), .RB(n111), .Q(RMIN[5]) ); DFERPQ1 \RMIN_reg[6] ( .D(DATA_IN[6]), .CEB(n72), .CK(CLOCK), .RB(n124), .Q(RMIN[6]) ); DFERPQ1 \RMIN_reg[7] ( .D(DATA_IN[7]), .CEB(n72), .CK(CLOCK), .RB(n124), .Q(RMIN[7]) ); DFERPQ1 \RLAST_reg[7] ( .D(N179), .CEB(n71), .CK(CLOCK), .RB(n123), .Q( RLAST[7]) ); DFERPQ1 \RLAST_reg[6] ( .D(N178), .CEB(n71), .CK(CLOCK), .RB(n110), .Q( RLAST[6]) ); DFERPQ1 \RLAST_reg[5] ( .D(N177), .CEB(n71), .CK(CLOCK), .RB(n123), .Q( RLAST[5]) ); DFERPQ1 \RLAST_reg[4] ( .D(N176), .CEB(n71), .CK(CLOCK), .RB(n123), .Q( RLAST[4]) ); DFERPQ1 \RLAST_reg[3] ( .D(N175), .CEB(n71), .CK(CLOCK), .RB(n121), .Q( RLAST[3]) ); DFERPQ1 \RLAST_reg[2] ( .D(N174), .CEB(n71), .CK(CLOCK), .RB(n111), .Q( RLAST[2]) ); DFERPQ1 \RLAST_reg[1] ( .D(N173), .CEB(n71), .CK(CLOCK), .RB(n121), .Q( RLAST[1]) ); DFERPQ1 \RLAST_reg[0] ( .D(N172), .CEB(n71), .CK(CLOCK), .RB(n121), .Q( RLAST[0]) ); DFERPQ1 \REG1_reg[7] ( .D(N179), .CEB(n117), .CK(CLOCK), .RB(n121), .Q( REG1[7]) ); DFERPQ1 \REG1_reg[6] ( .D(N178), .CEB(n119), .CK(CLOCK), .RB(n123), .Q( REG1[6]) ); DFERPQ1 \REG1_reg[5] ( .D(N177), .CEB(n118), .CK(CLOCK), .RB(n124), .Q( REG1[5]) ); DFERPQ1 \REG1_reg[4] ( .D(N176), .CEB(n117), .CK(CLOCK), .RB(n122), .Q( REG1[4]) ); DFERPQ1 \REG1_reg[3] ( .D(N175), .CEB(n119), .CK(CLOCK), .RB(n121), .Q( REG1[3]) ); DFERPQ1 \REG1_reg[2] ( .D(N174), .CEB(n118), .CK(CLOCK), .RB(n123), .Q( REG1[2]) ); DFERPQ1 \REG1_reg[1] ( .D(N173), .CEB(n117), .CK(CLOCK), .RB(n124), .Q( REG1[1]) ); DFERPQ1 \REG1_reg[0] ( .D(N172), .CEB(n119), .CK(CLOCK), .RB(n122), .Q( REG1[0]) ); DFERPQ1 \REG2_reg[7] ( .D(N187), .CEB(n119), .CK(CLOCK), .RB(n121), .Q( REG2[7]) ); DFERPQ1 \REG2_reg[6] ( .D(N186), .CEB(n118), .CK(CLOCK), .RB(n123), .Q( REG2[6]) ); DFERPQ1 \REG2_reg[5] ( .D(N185), .CEB(n117), .CK(CLOCK), .RB(n124), .Q( REG2[5]) ); DFERPQ1 \REG2_reg[4] ( .D(N184), .CEB(n119), .CK(CLOCK), .RB(n122), .Q( REG2[4]) ); DFERPQ1 \REG2_reg[3] ( .D(N183), .CEB(n118), .CK(CLOCK), .RB(n121), .Q( REG2[3]) ); DFERPQ1 \REG2_reg[2] ( .D(N182), .CEB(n117), .CK(CLOCK), .RB(n123), .Q( REG2[2]) ); DFERPQ1 \REG2_reg[1] ( .D(N181), .CEB(n119), .CK(CLOCK), .RB(n124), .Q( REG2[1]) ); DFERPQ1 \REG2_reg[0] ( .D(N180), .CEB(n118), .CK(CLOCK), .RB(n122), .Q( REG2[0]) ); DFERPQ1 \REG3_reg[7] ( .D(N195), .CEB(n118), .CK(CLOCK), .RB(n111), .Q( REG3[7]) ); DFERPQ1 \REG3_reg[6] ( .D(N194), .CEB(n117), .CK(CLOCK), .RB(n110), .Q( REG3[6]) ); DFERPQ1 \REG3_reg[5] ( .D(N193), .CEB(n119), .CK(CLOCK), .RB(n111), .Q( REG3[5]) ); DFERPQ1 \REG3_reg[4] ( .D(N192), .CEB(n118), .CK(CLOCK), .RB(n110), .Q( REG3[4]) ); DFERPQ1 \REG3_reg[3] ( .D(N191), .CEB(n117), .CK(CLOCK), .RB(n111), .Q( REG3[3]) ); DFERPQ1 \REG3_reg[2] ( .D(N190), .CEB(n119), .CK(CLOCK), .RB(n110), .Q( REG3[2]) ); DFERPQ1 \REG3_reg[1] ( .D(N189), .CEB(n118), .CK(CLOCK), .RB(n111), .Q( REG3[1]) ); DFERPQ1 \REG3_reg[0] ( .D(N188), .CEB(n117), .CK(CLOCK), .RB(n110), .Q( REG3[0]) ); DFERPQ1 \REG4_reg[7] ( .D(N203), .CEB(n117), .CK(CLOCK), .RB(n121), .Q( REG4[7]) ); DFERPQ1 \REG4_reg[6] ( .D(N202), .CEB(n119), .CK(CLOCK), .RB(n123), .Q( REG4[6]) ); DFERPQ1 \REG4_reg[5] ( .D(N201), .CEB(n118), .CK(CLOCK), .RB(n124), .Q( REG4[5]) ); DFERPQ1 \REG4_reg[4] ( .D(N200), .CEB(n117), .CK(CLOCK), .RB(n122), .Q( REG4[4]) ); DFERPQ1 \REG4_reg[3] ( .D(N199), .CEB(n119), .CK(CLOCK), .RB(n121), .Q( REG4[3]) ); DFERPQ1 \REG4_reg[2] ( .D(N198), .CEB(n118), .CK(CLOCK), .RB(n123), .Q( REG4[2]) ); DFERPQ1 \REG4_reg[1] ( .D(N197), .CEB(n117), .CK(CLOCK), .RB(n124), .Q( REG4[1]) ); DFERPQ1 \REG4_reg[0] ( .D(N196), .CEB(n119), .CK(CLOCK), .RB(n122), .Q( REG4[0]) ); DFERPQ1 \DATA_OUT_reg[7] ( .D(N212), .CEB(n117), .CK(CLOCK), .RB(n122), .Q( DATA_OUT[7]) ); DFERPQ1 \DATA_OUT_reg[6] ( .D(N211), .CEB(n118), .CK(CLOCK), .RB(n110), .Q( DATA_OUT[6]) ); DFERPQ1 \DATA_OUT_reg[5] ( .D(N210), .CEB(n119), .CK(CLOCK), .RB(n122), .Q( DATA_OUT[5]) ); DFERPQ1 \DATA_OUT_reg[4] ( .D(N209), .CEB(n117), .CK(CLOCK), .RB(n122), .Q( DATA_OUT[4]) ); DFERPQ1 \DATA_OUT_reg[3] ( .D(N208), .CEB(n118), .CK(CLOCK), .RB(n124), .Q( DATA_OUT[3]) ); DFERPQ1 \DATA_OUT_reg[2] ( .D(N207), .CEB(n119), .CK(CLOCK), .RB(n111), .Q( DATA_OUT[2]) ); DFERPQ1 \DATA_OUT_reg[1] ( .D(N206), .CEB(n117), .CK(CLOCK), .RB(n124), .Q( DATA_OUT[1]) ); DFERPQ1 \DATA_OUT_reg[0] ( .D(N205), .CEB(n118), .CK(CLOCK), .RB(n124), .Q( DATA_OUT[0]) ); INVD0 U3 ( .A(N169), .Z(n70) ); INVD0 U4 ( .A(N204), .Z(n71) ); INVD0 U5 ( .A(N171), .Z(n72) ); INVD0 U6 ( .A(N170), .Z(n73) ); INVD0 U7 ( .A(RESET), .Z(n74) ); AND3D1 U16 ( .A1(N42), .A2(n75), .A3(N50), .Z(\U3/U5/Z_0 ) ); OAI22M22D1 U17 ( .A1(RMIN[7]), .A2(RESTART), .B1(REG4[7]), .B2(n108), .Z( \U3/U4/Z_8 ) ); OAI22M22D1 U18 ( .A1(RMAX[7]), .A2(RESTART), .B1(DATA_IN[7]), .B2(n107), .Z( \U3/U3/Z_8 ) ); OAI22M22D1 U19 ( .A1(RMIN[6]), .A2(RESTART), .B1(REG4[6]), .B2(n108), .Z( \U3/U4/Z_6 ) ); OAI22M22D1 U20 ( .A1(RMIN[5]), .A2(RESTART), .B1(REG4[5]), .B2(n107), .Z( \U3/U4/Z_5 ) ); OAI22M22D1 U21 ( .A1(RMIN[4]), .A2(RESTART), .B1(REG4[4]), .B2(n108), .Z( \U3/U4/Z_4 ) ); OAI22M22D1 U22 ( .A1(RMIN[3]), .A2(RESTART), .B1(REG4[3]), .B2(n107), .Z( \U3/U4/Z_3 ) ); OAI22M22D1 U23 ( .A1(RMIN[2]), .A2(RESTART), .B1(REG4[2]), .B2(n108), .Z( \U3/U4/Z_2 ) ); OAI22M22D1 U24 ( .A1(RMIN[1]), .A2(RESTART), .B1(REG4[1]), .B2(n107), .Z( \U3/U4/Z_1 ) ); OAI22M22D1 U25 ( .A1(RMIN[0]), .A2(RESTART), .B1(REG4[0]), .B2(n108), .Z( \U3/U4/Z_0 ) ); OAI22M22D1 U26 ( .A1(RMAX[6]), .A2(RESTART), .B1(DATA_IN[6]), .B2(n107), .Z( \U3/U3/Z_6 ) ); OAI22M22D1 U27 ( .A1(RMAX[5]), .A2(RESTART), .B1(DATA_IN[5]), .B2(n108), .Z( \U3/U3/Z_5 ) ); OAI22M22D1 U28 ( .A1(RMAX[4]), .A2(RESTART), .B1(DATA_IN[4]), .B2(n107), .Z( \U3/U3/Z_4 ) ); OAI22M22D1 U29 ( .A1(RMAX[3]), .A2(RESTART), .B1(DATA_IN[3]), .B2(n108), .Z( \U3/U3/Z_3 ) ); OAI22M22D1 U30 ( .A1(RMAX[2]), .A2(RESTART), .B1(DATA_IN[2]), .B2(n107), .Z( \U3/U3/Z_2 ) ); OAI22M22D1 U31 ( .A1(RMAX[1]), .A2(RESTART), .B1(DATA_IN[1]), .B2(n108), .Z( \U3/U3/Z_1 ) ); OAI22M22D1 U32 ( .A1(RMAX[0]), .A2(RESTART), .B1(DATA_IN[0]), .B2(n107), .Z( \U3/U3/Z_0 ) ); NOR3D1 U33 ( .A1(N77), .A2(RESTART), .A3(n77), .Z(n76) ); INVD0 U34 ( .A(N79), .Z(n77) ); AO222D1 U35 ( .A1(N141), .A2(n78), .B1(N124), .B2(n79), .C1(n80), .C2( REG4[7]), .Z(N212) ); AO222D1 U36 ( .A1(N142), .A2(n78), .B1(N123), .B2(n79), .C1(n80), .C2( REG4[6]), .Z(N211) ); OAI211D1 U37 ( .A1(n81), .A2(n82), .B(n83), .C(n84), .Z(N210) ); AOI22D1 U38 ( .A1(N87), .A2(n85), .B1(N122), .B2(n79), .Z(n84) ); NAN2D0 U39 ( .A1(N143), .A2(n78), .Z(n83) ); INVD0 U40 ( .A(REG4[5]), .Z(n81) ); OAI211D1 U41 ( .A1(n86), .A2(n82), .B(n87), .C(n88), .Z(N209) ); AOI22D1 U42 ( .A1(N86), .A2(n85), .B1(N121), .B2(n79), .Z(n88) ); NAN2D0 U43 ( .A1(N144), .A2(n78), .Z(n87) ); INVD0 U44 ( .A(REG4[4]), .Z(n86) ); OAI211D1 U45 ( .A1(n89), .A2(n82), .B(n90), .C(n91), .Z(N208) ); AOI22D1 U46 ( .A1(N85), .A2(n85), .B1(N120), .B2(n79), .Z(n91) ); NAN2D0 U47 ( .A1(N145), .A2(n78), .Z(n90) ); INVD0 U48 ( .A(REG4[3]), .Z(n89) ); OAI211D1 U49 ( .A1(n92), .A2(n82), .B(n93), .C(n94), .Z(N207) ); AOI22D1 U50 ( .A1(N84), .A2(n85), .B1(N119), .B2(n79), .Z(n94) ); NAN2D0 U51 ( .A1(N146), .A2(n78), .Z(n93) ); INVD0 U52 ( .A(REG4[2]), .Z(n92) ); OAI211D1 U53 ( .A1(n95), .A2(n82), .B(n96), .C(n97), .Z(N206) ); AOI22D1 U54 ( .A1(N83), .A2(n85), .B1(N118), .B2(n79), .Z(n97) ); NAN2D0 U55 ( .A1(N147), .A2(n78), .Z(n96) ); INVD0 U56 ( .A(REG4[1]), .Z(n95) ); OAI211D1 U57 ( .A1(n98), .A2(n82), .B(n99), .C(n100), .Z(N205) ); AOI22D1 U58 ( .A1(N82), .A2(n85), .B1(N117), .B2(n79), .Z(n100) ); NOR3D1 U59 ( .A1(n101), .A2(N40), .A3(n102), .Z(n79) ); AND3D1 U60 ( .A1(n115), .A2(n75), .A3(N40), .Z(n85) ); INVD0 U61 ( .A(n101), .Z(n75) ); AOI21D1 U62 ( .A1(n103), .A2(N79), .B(RESTART), .Z(n101) ); NAN2D0 U63 ( .A1(N148), .A2(n78), .Z(n99) ); NOR3D1 U64 ( .A1(n102), .A2(RESTART), .A3(n103), .Z(n78) ); INVD0 U65 ( .A(N77), .Z(n103) ); INVD0 U66 ( .A(n80), .Z(n82) ); NOR4D1 U67 ( .A1(n102), .A2(N77), .A3(N79), .A4(RESTART), .Z(n80) ); INVD0 U68 ( .A(REG4[0]), .Z(n98) ); OAI21D1 U69 ( .A1(N77), .A2(n102), .B(n104), .Z(N204) ); AND2D0 U70 ( .A1(REG3[7]), .A2(n114), .Z(N203) ); AND2D0 U71 ( .A1(REG3[6]), .A2(n115), .Z(N202) ); AND2D0 U72 ( .A1(REG3[5]), .A2(n113), .Z(N201) ); AND2D0 U73 ( .A1(REG3[4]), .A2(n114), .Z(N200) ); AND2D0 U74 ( .A1(REG3[3]), .A2(n115), .Z(N199) ); AND2D0 U75 ( .A1(REG3[2]), .A2(n113), .Z(N198) ); AND2D0 U76 ( .A1(REG3[1]), .A2(n114), .Z(N197) ); AND2D0 U77 ( .A1(REG3[0]), .A2(n115), .Z(N196) ); AND2D0 U78 ( .A1(REG2[7]), .A2(n113), .Z(N195) ); AND2D0 U79 ( .A1(REG2[6]), .A2(n114), .Z(N194) ); AND2D0 U80 ( .A1(REG2[5]), .A2(n115), .Z(N193) ); AND2D0 U81 ( .A1(REG2[4]), .A2(n113), .Z(N192) ); AND2D0 U82 ( .A1(REG2[3]), .A2(n114), .Z(N191) ); AND2D0 U83 ( .A1(REG2[2]), .A2(n115), .Z(N190) ); NAN2M1D1 U84 ( .A1(stato[0]), .A2(stato[1]), .Z(N19) ); AND2D0 U85 ( .A1(REG2[1]), .A2(n113), .Z(N189) ); AND2D0 U86 ( .A1(REG2[0]), .A2(n114), .Z(N188) ); AND2D0 U87 ( .A1(REG1[7]), .A2(n115), .Z(N187) ); AND2D0 U88 ( .A1(REG1[6]), .A2(n113), .Z(N186) ); AND2D0 U89 ( .A1(REG1[5]), .A2(n114), .Z(N185) ); AND2D0 U90 ( .A1(REG1[4]), .A2(n115), .Z(N184) ); AND2D0 U91 ( .A1(REG1[3]), .A2(n113), .Z(N183) ); AND2D0 U92 ( .A1(REG1[2]), .A2(n114), .Z(N182) ); AND2D0 U93 ( .A1(REG1[1]), .A2(n115), .Z(N181) ); AND2D0 U94 ( .A1(REG1[0]), .A2(n113), .Z(N180) ); AND2D0 U95 ( .A1(DATA_IN[7]), .A2(n114), .Z(N179) ); AND2D0 U96 ( .A1(DATA_IN[6]), .A2(n115), .Z(N178) ); AND2D0 U97 ( .A1(DATA_IN[5]), .A2(n113), .Z(N177) ); AND2D0 U98 ( .A1(DATA_IN[4]), .A2(n114), .Z(N176) ); AND2D0 U99 ( .A1(DATA_IN[3]), .A2(n115), .Z(N175) ); AND2D0 U100 ( .A1(DATA_IN[2]), .A2(n113), .Z(N174) ); AND2D0 U101 ( .A1(DATA_IN[1]), .A2(n114), .Z(N173) ); AND2D0 U102 ( .A1(DATA_IN[0]), .A2(n115), .Z(N172) ); OAI31M30D1 U103 ( .A1(n114), .A2(n105), .A3(N167), .B(n104), .Z(N171) ); OAI21D1 U104 ( .A1(n102), .A2(n105), .B(n104), .Z(N170) ); INVD0 U105 ( .A(N18), .Z(n104) ); INVD0 U106 ( .A(N165), .Z(n105) ); INVD0 U107 ( .A(n113), .Z(n102) ); NAN2M1D1 U108 ( .A1(stato[1]), .A2(stato[0]), .Z(N17) ); NOR2D0 U109 ( .A1(stato[1]), .A2(stato[0]), .Z(N16) ); ADFULD1 \r174/U1_8 ( .A(\U3/U3/Z_8 ), .B(\U3/U4/Z_8 ), .CI(\r174/carry[8] ), .S(N39) ); ADFULD1 \r33/U1_1 ( .A(\U3/U3/Z_1 ), .B(\U3/U4/Z_1 ), .CI(\r33/carry[1] ), .CO(\r33/carry[2] ), .S(N82) ); ADFULD1 \r33/U1_2 ( .A(\U3/U3/Z_2 ), .B(\U3/U4/Z_2 ), .CI(\r33/carry[2] ), .CO(\r33/carry[3] ), .S(N83) ); ADFULD1 \r33/U1_3 ( .A(\U3/U3/Z_3 ), .B(\U3/U4/Z_3 ), .CI(\r33/carry[3] ), .CO(\r33/carry[4] ), .S(N84) ); ADFULD1 \r33/U1_4 ( .A(\U3/U3/Z_4 ), .B(\U3/U4/Z_4 ), .CI(\r33/carry[4] ), .CO(\r33/carry[5] ), .S(N85) ); ADFULD1 \r33/U1_5 ( .A(\U3/U3/Z_5 ), .B(\U3/U4/Z_5 ), .CI(\r33/carry[5] ), .CO(\r33/carry[6] ), .S(N86) ); ADFULD1 \r33/U1_6 ( .A(\U3/U3/Z_6 ), .B(\U3/U4/Z_6 ), .CI(\r33/carry[6] ), .S(N87) ); INVD0 U110 ( .A(n76), .Z(n106) ); INVD0 U111 ( .A(n106), .Z(n107) ); INVD0 U112 ( .A(n106), .Z(n108) ); INVD0 U113 ( .A(n124), .Z(n109) ); INVD0 U114 ( .A(n109), .Z(n110) ); INVD0 U115 ( .A(n109), .Z(n111) ); INVD0 U116 ( .A(N20), .Z(n112) ); INVD0 U117 ( .A(n112), .Z(n113) ); INVD0 U118 ( .A(n112), .Z(n114) ); INVD0 U119 ( .A(n112), .Z(n115) ); INVD0 U120 ( .A(n70), .Z(n116) ); INVD0 U121 ( .A(n116), .Z(n117) ); INVD0 U122 ( .A(n116), .Z(n118) ); INVD0 U123 ( .A(n116), .Z(n119) ); INVD0 U124 ( .A(n74), .Z(n120) ); INVD0 U125 ( .A(n120), .Z(n121) ); INVD0 U126 ( .A(n120), .Z(n122) ); INVD0 U127 ( .A(n120), .Z(n123) ); INVD0 U128 ( .A(n120), .Z(n124) ); NOR2D4 U129 ( .A1(n125), .A2(n126), .Z(\r34/carry[1] ) ); INVD4 U130 ( .A(\r34/carry[0] ), .Z(n125) ); INVD4 U131 ( .A(\r34/B_not[0] ), .Z(n126) ); EXOR2D2 U132 ( .A1(\r34/B_not[0] ), .A2(\r34/carry[0] ), .Z(N117) ); NOR2D4 U133 ( .A1(n127), .A2(n128), .Z(\r34/carry[2] ) ); INVD4 U134 ( .A(\r34/carry[1] ), .Z(n127) ); INVD4 U135 ( .A(\r34/B_not[1] ), .Z(n128) ); EXOR2D2 U136 ( .A1(\r34/B_not[1] ), .A2(\r34/carry[1] ), .Z(N118) ); NOR2D4 U137 ( .A1(n129), .A2(n130), .Z(\r34/carry[3] ) ); INVD4 U138 ( .A(\r34/carry[2] ), .Z(n129) ); INVD4 U139 ( .A(\r34/B_not[2] ), .Z(n130) ); EXOR2D2 U140 ( .A1(\r34/B_not[2] ), .A2(\r34/carry[2] ), .Z(N119) ); NOR2D4 U141 ( .A1(n131), .A2(n132), .Z(\r34/carry[4] ) ); INVD4 U142 ( .A(\r34/carry[3] ), .Z(n131) ); INVD4 U143 ( .A(\r34/B_not[3] ), .Z(n132) ); EXOR2D2 U144 ( .A1(\r34/B_not[3] ), .A2(\r34/carry[3] ), .Z(N120) ); NOR2D4 U145 ( .A1(n133), .A2(n134), .Z(\r34/carry[5] ) ); INVD4 U146 ( .A(\r34/carry[4] ), .Z(n133) ); INVD4 U147 ( .A(\r34/B_not[4] ), .Z(n134) ); EXOR2D2 U148 ( .A1(\r34/B_not[4] ), .A2(\r34/carry[4] ), .Z(N121) ); NOR2D4 U149 ( .A1(n135), .A2(n136), .Z(\r34/carry[6] ) ); INVD4 U150 ( .A(\r34/carry[5] ), .Z(n135) ); INVD4 U151 ( .A(\r34/B_not[5] ), .Z(n136) ); EXOR2D2 U152 ( .A1(\r34/B_not[5] ), .A2(\r34/carry[5] ), .Z(N122) ); NOR2D4 U153 ( .A1(n137), .A2(n138), .Z(\r34/carry[7] ) ); INVD4 U154 ( .A(\r34/carry[6] ), .Z(n137) ); INVD4 U155 ( .A(\r34/B_not[6] ), .Z(n138) ); EXOR2D2 U156 ( .A1(\r34/B_not[6] ), .A2(\r34/carry[6] ), .Z(N123) ); EXOR2D2 U157 ( .A1(\r34/B_not[7] ), .A2(\r34/carry[7] ), .Z(N124) ); NOR2D4 U158 ( .A1(n139), .A2(n140), .Z(\r176/carry[2] ) ); INVD4 U159 ( .A(\r176/carry[1] ), .Z(n139) ); INVD4 U160 ( .A(\r176/B_not[1] ), .Z(n140) ); EXOR2D2 U161 ( .A1(\r176/B_not[1] ), .A2(\r176/carry[1] ), .Z(N100) ); NOR2D4 U162 ( .A1(n141), .A2(n142), .Z(\r176/carry[3] ) ); INVD4 U163 ( .A(\r176/carry[2] ), .Z(n141) ); INVD4 U164 ( .A(\r176/B_not[2] ), .Z(n142) ); EXOR2D2 U165 ( .A1(\r176/B_not[2] ), .A2(\r176/carry[2] ), .Z(N101) ); NOR2D4 U166 ( .A1(n143), .A2(n144), .Z(\r176/carry[4] ) ); INVD4 U167 ( .A(\r176/carry[3] ), .Z(n143) ); INVD4 U168 ( .A(\r176/B_not[3] ), .Z(n144) ); EXOR2D2 U169 ( .A1(\r176/B_not[3] ), .A2(\r176/carry[3] ), .Z(N102) ); NOR2D4 U170 ( .A1(n145), .A2(n146), .Z(\r176/carry[5] ) ); INVD4 U171 ( .A(\r176/carry[4] ), .Z(n145) ); INVD4 U172 ( .A(\r176/B_not[4] ), .Z(n146) ); EXOR2D2 U173 ( .A1(\r176/B_not[4] ), .A2(\r176/carry[4] ), .Z(N103) ); NOR2D4 U174 ( .A1(n147), .A2(n148), .Z(\r176/carry[6] ) ); INVD4 U175 ( .A(\r176/carry[5] ), .Z(n147) ); INVD4 U176 ( .A(\r176/B_not[5] ), .Z(n148) ); EXOR2D2 U177 ( .A1(\r176/B_not[5] ), .A2(\r176/carry[5] ), .Z(N104) ); NOR2D4 U178 ( .A1(n149), .A2(n150), .Z(\r176/carry[7] ) ); INVD4 U179 ( .A(\r176/carry[6] ), .Z(n149) ); INVD4 U180 ( .A(\r176/B_not[6] ), .Z(n150) ); EXOR2D2 U181 ( .A1(\r176/B_not[6] ), .A2(\r176/carry[6] ), .Z(N105) ); NOR2D4 U182 ( .A1(n151), .A2(n152), .Z(\r33/carry[1] ) ); INVD4 U183 ( .A(\U3/U3/Z_0 ), .Z(n151) ); INVD4 U184 ( .A(\U3/U4/Z_0 ), .Z(n152) ); EXOR2D2 U185 ( .A1(\U3/U4/Z_0 ), .A2(\U3/U3/Z_0 ), .Z(N42) ); INVD0 U186 ( .A(RMAX[7]), .Z(n168) ); AND2D0 U187 ( .A1(n168), .A2(DATA_IN[7]), .Z(n167) ); INVD0 U188 ( .A(RMAX[6]), .Z(n165) ); INVD0 U189 ( .A(DATA_IN[6]), .Z(n163) ); INVD0 U190 ( .A(DATA_IN[5]), .Z(n162) ); INVD0 U191 ( .A(DATA_IN[4]), .Z(n160) ); INVD0 U192 ( .A(DATA_IN[3]), .Z(n158) ); INVD0 U193 ( .A(DATA_IN[2]), .Z(n156) ); NAN2M1D1 U194 ( .A1(RMAX[0]), .A2(DATA_IN[0]), .Z(n154) ); AOI21M20D1 U195 ( .A1(n154), .A2(RMAX[1]), .B(DATA_IN[1]), .Z(n153) ); AO221D1 U196 ( .A1(RMAX[2]), .A2(n156), .B1(RMAX[1]), .B2(n154), .C(n153), .Z(n155) ); OA221D1 U197 ( .A1(n158), .A2(RMAX[3]), .B1(n156), .B2(RMAX[2]), .C(n155), .Z(n157) ); AO221D1 U198 ( .A1(RMAX[4]), .A2(n160), .B1(RMAX[3]), .B2(n158), .C(n157), .Z(n159) ); OA221D1 U199 ( .A1(n162), .A2(RMAX[5]), .B1(n160), .B2(RMAX[4]), .C(n159), .Z(n161) ); AOI221D1 U200 ( .A1(RMAX[6]), .A2(n163), .B1(RMAX[5]), .B2(n162), .C(n161), .Z(n164) ); AOI21D1 U201 ( .A1(DATA_IN[6]), .A2(n165), .B(n164), .Z(n166) ); OAI22D1 U202 ( .A1(DATA_IN[7]), .A2(n168), .B1(n167), .B2(n166), .Z(N165) ); OA211D1 U203 ( .A1(\U3/U3/Z_1 ), .A2(\U3/U4/Z_1 ), .B(\U3/U3/Z_0 ), .C( \U3/U4/Z_0 ), .Z(n171) ); AOI21D1 U204 ( .A1(\U3/U3/Z_1 ), .A2(\U3/U4/Z_1 ), .B(n171), .Z(n173) ); OAI21M10D1 U205 ( .A1(n173), .A2(\U3/U3/Z_2 ), .B(\U3/U4/Z_2 ), .Z(n172) ); OAI21M10D1 U206 ( .A1(\U3/U3/Z_2 ), .A2(n173), .B(n172), .Z(n175) ); OA21D1 U207 ( .A1(\U3/U3/Z_3 ), .A2(n175), .B(\U3/U4/Z_3 ), .Z(n174) ); AOI21D1 U208 ( .A1(n175), .A2(\U3/U3/Z_3 ), .B(n174), .Z(n177) ); OAI21M10D1 U209 ( .A1(n177), .A2(\U3/U3/Z_4 ), .B(\U3/U4/Z_4 ), .Z(n176) ); OAI21M10D1 U210 ( .A1(\U3/U3/Z_4 ), .A2(n177), .B(n176), .Z(n179) ); OA21D1 U211 ( .A1(\U3/U3/Z_5 ), .A2(n179), .B(\U3/U4/Z_5 ), .Z(n178) ); AOI21D1 U212 ( .A1(n179), .A2(\U3/U3/Z_5 ), .B(n178), .Z(n181) ); OAI21M10D1 U213 ( .A1(n181), .A2(\U3/U3/Z_6 ), .B(\U3/U4/Z_6 ), .Z(n180) ); OAI21M10D1 U214 ( .A1(\U3/U3/Z_6 ), .A2(n181), .B(n180), .Z(n183) ); OAI21D1 U215 ( .A1(\U3/U3/Z_8 ), .A2(n183), .B(\U3/U4/Z_8 ), .Z(n182) ); OAI21M20D1 U216 ( .A1(n183), .A2(\U3/U3/Z_8 ), .B(n182), .Z(\r174/carry[8] ) ); INVD0 U217 ( .A(N39), .Z(N40) ); INVD0 U218 ( .A(N82), .Z(\r176/B_not[1] ) ); INVD0 U219 ( .A(N83), .Z(\r176/B_not[2] ) ); INVD0 U220 ( .A(N84), .Z(\r176/B_not[3] ) ); INVD0 U221 ( .A(N85), .Z(\r176/B_not[4] ) ); INVD0 U222 ( .A(N86), .Z(\r176/B_not[5] ) ); INVD0 U223 ( .A(N87), .Z(\r176/B_not[6] ) ); INVD0 U224 ( .A(\r176/carry[7] ), .Z(N50) ); INVD0 U225 ( .A(N42), .Z(\r176/carry[1] ) ); INVD0 U226 ( .A(N100), .Z(\r34/B_not[0] ) ); INVD0 U227 ( .A(N101), .Z(\r34/B_not[1] ) ); INVD0 U228 ( .A(N102), .Z(\r34/B_not[2] ) ); INVD0 U229 ( .A(N103), .Z(\r34/B_not[3] ) ); INVD0 U230 ( .A(N104), .Z(\r34/B_not[4] ) ); INVD0 U231 ( .A(N105), .Z(\r34/B_not[5] ) ); INVD0 U232 ( .A(N50), .Z(\r34/B_not[6] ) ); INVD0 U233 ( .A(N50), .Z(\r34/B_not[7] ) ); INVD0 U234 ( .A(\U3/U5/Z_0 ), .Z(\r34/carry[0] ) ); INVD0 U235 ( .A(DATA_IN[7]), .Z(n199) ); AND2D0 U236 ( .A1(n199), .A2(RMIN[7]), .Z(n198) ); INVD0 U237 ( .A(DATA_IN[6]), .Z(n196) ); INVD0 U238 ( .A(RMIN[6]), .Z(n194) ); INVD0 U239 ( .A(RMIN[5]), .Z(n193) ); INVD0 U240 ( .A(RMIN[4]), .Z(n191) ); INVD0 U241 ( .A(RMIN[3]), .Z(n189) ); INVD0 U242 ( .A(RMIN[2]), .Z(n187) ); NAN2M1D1 U243 ( .A1(DATA_IN[0]), .A2(RMIN[0]), .Z(n185) ); AOI21M20D1 U244 ( .A1(n185), .A2(DATA_IN[1]), .B(RMIN[1]), .Z(n184) ); AO221D1 U245 ( .A1(DATA_IN[2]), .A2(n187), .B1(DATA_IN[1]), .B2(n185), .C( n184), .Z(n186) ); OA221D1 U246 ( .A1(n189), .A2(DATA_IN[3]), .B1(n187), .B2(DATA_IN[2]), .C( n186), .Z(n188) ); AO221D1 U247 ( .A1(DATA_IN[4]), .A2(n191), .B1(DATA_IN[3]), .B2(n189), .C( n188), .Z(n190) ); OA221D1 U248 ( .A1(n193), .A2(DATA_IN[5]), .B1(n191), .B2(DATA_IN[4]), .C( n190), .Z(n192) ); AOI221D1 U249 ( .A1(DATA_IN[6]), .A2(n194), .B1(DATA_IN[5]), .B2(n193), .C( n192), .Z(n195) ); AOI21D1 U250 ( .A1(RMIN[6]), .A2(n196), .B(n195), .Z(n197) ); OAI22D1 U251 ( .A1(RMIN[7]), .A2(n199), .B1(n198), .B2(n197), .Z(N167) ); endmodule
I will attach the verilog code.
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