Bit Reversing in VHDL

[SharpWeapon]

Hello,

What is wrong with ISE compiler? The following code should work without any problem.

A: in STD_LOGIC_VECTOR(3 downto 0);
output: out STD_LOGIC_VECTOR(3 downto 0)
....
output(3 downto 0)<=A(0 to 3);
output(0 to 3)<=A(3 downto 0);

But it generates the following error in either way:

 Slice direction differs from its index subtype range

PS: It doesn't generate an error if I change

A: in STD_LOGIC_VECTOR(0 to 3);

But that is not what I wanted which it only copied the result without reversing.

 

[TrickyDicky]

In VHDL, you cannot access an array delcared donto by slicing it with a downto direction, and vice versa.

 

[SharpWeapon]

Hey TrickyDicky, so do I have to use loop just to do such simple task? There should have been a built-in function or sth. A big fail!

 

[TrickyDicky]

The question is why are you reversing it?
Why not just declare A as

a : in std_logic_vector(0 to 3);
op : out std_logic_vector(3 downto 0);

then you can assign:

op <= a; --0 connects to 3, 1 to 2, 2 to 1 and 3 to 0

Most people never flip busses - why would you need to?>

 

[std_match]

If "output" is declared as (0 to 3) and A is declared as (3 downto 0) you can assign directly between them.

output <= A;

output(0) will be assigned from A(3) etc.

Does that help you?

Edit:
too late, TrickyDicky just posted the same information.

 

[SharpWeapon]

I am sorry but the suggested solution is ONLY COPYING the content of the signal. It is not reversing it.
What it is supposed to do is: given A="1000", reverseA="0001";

 

[std_match]

If "output" is connected to pins of the FPGA, the suggested solution will work.
If you for some reason really need to reverse the positions of the bits, a loop is the way to go.

 

[SharpWeapon]

I have a memory which I don't want to read in a normal addressing order, I want to read in bit reversed order of the normal addressing. In this case I am option-less right here, I will go for the loop if I don't come up with a new idea.

 

[std_match]

I have a memory which I don't want to read in a normal addressing order, I want to read in bit reversed order of the normal addressing. In this case I am option-less right here, I will go for the loop if I don't come up with a new idea.

You should use the loop. Unlike software loops, this loop will cost you nothing. It will not consume any hardware resources in the FPGA and it will not reduce the speed of the circuit. I't 3 lines of code that come completely free!

Bit-reversed addressing in software is a mess, but it is really easy in hardware.

 

[ads-ee]

Or you can brute force it (which I like to do sometimes as it's obvious)

A: in std_logic_vector(3 downto 0);
output: out std_logic_vector(3 downto 0);

-- bit reversal
output <= A(0) & A(1) & A(2) & A(3);

It's also only 1 line of code and will compile infinitesimally faster (no for loop to unravel) ;-)

 

[SharpWeapon]

ads-ee;1362124]Or you can brute force it (which I like to do sometimes as it's obvious)

Good suggestion if you are working with less bit width, but I am working on 36 bit width, not convenient in this case I guess. As std_match suggested, the loop works wonder in this case, I already wrote a reverse function for it and it is completely fine as it is not going to be processed in the FPGA. Thank you guys!