The rest of the post is missing.
There was a paragraph above the code section that included ' dis is d PSEUDO CODE' ,.
But it should be clear that it is 'PSEUDO'
'if somevariable_bitposition',
Obviously neither verilog/VHDL
Yep, there is a mixture, I had two projects open , VHDL/ Vlog , debugging an FPGA SATA interface with a broken JTag Cable which requires a finger, plus I was dealing with a SF-Express and an aliexpress seller on chat..
The rest of my post is obviously included in the cut & paste to Ali-express……