-= BIST & Memories =-

[ivlsi]

Hi All,

While compiling a RAM Memory, is it possible to choose whether it will or not contain the BIST?

Are there free tools on the market, which are able to generate BIST logic?

What consideration should usually be taken into account while creation BIST logic?

Thank you!

 

[rca]

The compiler propose to add another port for BIST hardware, but normally never the BIST itself.
I don't Know free tool.
How many memories by hardware BIST, one multiple?, you need to estimate the bIST test time, if you do in parallels of other test...

 

[ivlsi]

rca,

"I don't Know free tool" - so, what tools can generate BIST for the memory? which of them would you recommend?

As for the BIST Controller, is it always the same (from design to design)? If I want to test several memories in parallel, should I have several BIST Controllers?

As far as I know, there is not necessary to generate a BIST for each memory - a single BIST might be shared by several memories or, in another words, memories on the chip might be grouped for a single BIST usage. Is that correct? Could you please give more details?

"you need to estimate the bIST test time" - how could I do so? BIST works on several algorithms, which are not trivial at all... How this estimation might be done?

Thank you in advance for your response!

---------- Post added at 13:00 ---------- Previous post was at 12:46 ----------

What consideration should usually be taken into account while creation BIST logic?

---------- Post added at 13:32 ---------- Previous post was at 13:00 ----------

Could several Memories be tested in parallel by a single BIST Controller?

 

[rca]

Tessent tool from mentor could generate BIST. synopses and cadence some one also.
The number of read and write indicate you how much clock cycle is required then with your frequency you know the test time.
If you have one engine for multiple memories you will serialized the BIST.

 

[ivlsi]

"If you have one engine for multiple memories you will serialized the BIST" - does it mean that BIST Controller will test Memories one-by-one or it will see them as a single big Memory?

How big area does the BIST add (let's say in % of the tested SRAM area)?

Thank you!