[SOLVED] Bipolar Dac I-V converter and LtSpice simulation

[little0192]

Hi,
I am designing a +/- 10V output DAC board using a current output DAC (PN : AD9767ASTZ).
So I am already using a reference design for a Evaluation Board from here. The board can be configured for the different outputs. I am interested in the 3rd type for making +/- 10V signal output.

My first question is why they haven't used the 50 ohm parallel termination on the IoutA and IoutB. How is this series arrangement (in the Figure 9 above) functionally different from the parallel termination. However, In the LTC1668 datasheet the suggested circuit has parallel termination only.

Secondly, I am trying to simulate the circuit in the LTSpice to understand it better. But I am not getting the expected result. Can anyone guide/tell me what I am missing in the simulation? I am using a current source to emulate the Complimentary current output of 0-20mA.
I am attaching the LtSpice Simlation file as well. Thanks.

 

[BigBoss]

Try to use 2 Current Source that are connected in symmetrical configuration.
Sweep current value from 0-10mA for each..

 

[dick_freebird]

If you treat the op amp + R4 as a transimpedance amp
then its closed loop transimpedance is 1K and your
20mA input crest current should make a -20V output,
well greater than the +/-12V op amps can follow. To
this you are also adding 10mA from the VREF (which
would at crest drive you to -30V). What you probably
are seeing, is that only the lowest currents can be
amplified without clipping in the first stage, and the
clipped signal can't be restored by the second stage
offset.

Lower DAC current, or constrain first stage to remain
linear with max DAC current, and make it up in the
second stage?

 

[little0192]

Try to use 2 Current Source that are connected in symmetrical configuration.
Sweep current value from 0-10mA for each..

Thank for replying.
I added the two current sources as you said but still not getting the result. Is there any other configuration I can try? Thanks.

--- Updated Jul 1, 2020 ---

If you treat the op amp + R4 as a transimpedance amp
then its closed loop transimpedance is 1K and your
20mA input crest current should make a -20V output,
well greater than the +/-12V op amps can follow. To
this you are also adding 10mA from the VREF (which
would at crest drive you to -30V). What you probably
are seeing, is that only the lowest currents can be
amplified without clipping in the first stage, and the
clipped signal can't be restored by the second stage
offset.

Lower DAC current, or constrain first stage to remain
linear with max DAC current, and make it up in the
second stage?

yes I am getting what you are saying. If I reduce the current to 5mA then I am getting sine wave-output. But that means that the circuit is not using the full scale current output from the DAC. In the manual they did not mentioned the functionality.
Since this circuit is already verified I think I may be wrong with the implementation of the current output from the DAC.
Can you suggest me what should I try next? Thanks.

--- Updated Jul 1, 2020 ---

Try to use 2 Current Source that are connected in symmetrical configuration.
Sweep current value from 0-10mA for each..

Here is the LTSpice file.

 

[BigBoss]

There might be some problems in macro-model of the Op Amp.

 

[little0192]

There might be some problems in macro-model of the Op Amp.

Spice model is working fine. I checked with the test jig example.

--- Updated Jul 7, 2020 ---

So as I suspected that I am doing something wrong with the current sources. I looked once again at the DAC datasheet and found out that it is a current sink device. That means the IOutA pin actually sinks the current, the current is sourced from the op-amp output.
Also the complimentary output means that when IoutA is sinking 8mA current the pin IoutB will be sinking 2mA for a full scale current of 10mA. See the below image for reference.

Now getting clean waveforms.

Input Current

Thanks, I appreciate the help.