I am not sure I understand the question but I will explain what I think binning is.
Binning is used by foundries where they cannot match the models over a very wide range of devices sizes, so they match groups of sizes. So, one model would be used for, say, up to W=0.4um L=0.25um. The next model used up to W=0.8um and so on. Provided your simulator supports binning (I think it was devised by HSpice) then the process should be transparent to you. You will get a simulator error if a suitable model cannot be found - if the transistor is smaller or larger than there is a model for, or if the aspect ratio of the transistor is too large/small. You can usually get round such problems by using transistors in parallel, usually using the M parameter.
I don't know if it is still used - I don't often come across binned models nowadays.
Keith.