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Binary to decimal converter question.

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tvu1020

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Hello, I'm working on a little project called binary to decimal converter.
I use 4 push buttons as my 4 bits binary input. 7 segment display is my decimal output.The board i'm using is Basys2, and when I tried to synthesis it, it said the port "btn" is never connected and left unused.
Could anyone give me some advice? Here's the code and the constraints file

Code: 
module binaryconverter(clk,btn, AN, segA, segB, segC, segD, segE, segF, segG,segDP);
input clk;
input [3:0]btn;
output  reg [3:0]AN;
output   reg segA, segB, segC, segD, segE, segF, segG,segDP;


always @(btn)
   begin
   AN = 4'b1110;
{segA, segB, segC, segD, segE, segF, segG, segDP} = 8'b00100101;
   end

endmodule


constraint file
Code: 
NET clk LOC=B8;

NET btn<3> LOC=A7;
NET btn<2> LOC=M4;
NET btn<1> LOC=C11;
NET btn<0> LOC=G12;


NET AN<3> LOC=K14;
NET AN<2> LOC=M13;
NET AN<1> LOC=J12;
NET AN<0> LOC=F12;
 

it said the port "btn" is never connected
Click to expand...
Hard to disagree! Don't you feel a need to define different output codings for each binary value represented by input btn?
 

Sorry please bare with me, I only been learning FPGA for 2 weeks...I thought I set the values to 7segment every time I press the btn (alway@)
 

You should try something like
Code: 
always @(btn)
begin
  case (btn)
  4'b0000:
    {segA, segB, segC, segD, segE, segF, segG, segDP} =...
  4'b0001:
    {segA, segB, segC, segD, segE, segF, segG, segDP} =...
....

....
  default:
    {segA, segB, segC, segD, segE, segF, segG, segDP} =...
  endcase
end
 
I understood what you meant now! Thank you!

---------- Post added at 22:46 ---------- Previous post was at 21:19 ----------

When the buttons add up to value of 10. I tried to enable AN to display 2 digits in order to display 10 on the SSD. I seem to get the same values on 2 digits instead of 10. any advice? thanks

---------- Post added 28-09-11 at 00:33 ---------- Previous post was 27-09-11 at 22:46 ----------

Here is what i have got so far. THe delay function is to switch "data" between 0 and 1 really fast so that it looks like it display 2 digits SSD, but only turn on 1 SSD at a time. I thought that way it could display value 10 but somehow i think I only enable the 2 SSD and have the same value on both. PLease help!
Code: 
module binaryconverter(clk,btn, AN, segA, segB, segC, segD, segE, segF, segG,segDP);
input clk;
input [3:0]btn;
output  reg [3:0]AN;
output   reg segA, segB, segC, segD, segE, segF, segG,segDP;
reg [1:0] data;
reg [24:0] delay;
reg [3:0] digit1, digit2;



always @(posedge clk)begin
if (data == 0)
begin
	AN = 4'b1110;	
	case (digit1)	
4'b0000: {segA, segB, segC, segD, segE, segF, segG, segDP} = 8'b00000010;
4'b0001: {segA, segB, segC, segD, segE, segF, segG, segDP} = 8'b10011111; //single digit
4'b0010: {segA, segB, segC, segD, segE, segF, segG, segDP} = 8'b00100101;
4'b0011: {segA, segB, segC, segD, segE, segF, segG, segDP} = 8'b00001101;
4'b0100: {segA, segB, segC, segD, segE, segF, segG, segDP} = 8'b10011001;
4'b0101: {segA, segB, segC, segD, segE, segF, segG, segDP} = 8'b01001001;
4'b0110: {segA, segB, segC, segD, segE, segF, segG, segDP} = 8'b01000001;
4'b0111: {segA, segB, segC, segD, segE, segF, segG, segDP} = 8'b00011111;
4'b1000: {segA, segB, segC, segD, segE, segF, segG, segDP} = 8'b00000001;
4'b1001: {segA, segB, segC, segD, segE, segF, segG, segDP} = 8'b00001001;
default: {segA, segB, segC, segD, segE, segF, segG, segDP} = 8'b10011111;
	endcase
end
if (data == 1)
begin
AN = 4'b1101;
	case (digit2)
4'b1010: {segA, segB, segC, segD, segE, segF, segG, segDP} = 8'b10011111; //double digits
4'b1011: {segA, segB, segC, segD, segE, segF, segG, segDP} = 8'b10011111;
4'b1100: {segA, segB, segC, segD, segE, segF, segG, segDP} = 8'b10011111;
4'b1101: {segA, segB, segC, segD, segE, segF, segG, segDP} = 8'b10011111;
4'b1110: {segA, segB, segC, segD, segE, segF, segG, segDP} = 8'b10011111;
4'b1111: {segA, segB, segC, segD, segE, segF, segG, segDP} = 8'b10011111;

	endcase
end

if (!delay[17:0])data = data + 1;
if (data >= 2) data = 0 ;
 delay= delay +1;
end
endmodule


---------- Post added at 00:34 ---------- Previous post was at 00:33 ----------

Here is what i have got so far. THe delay function is to switch "data" between 0 and 1 really fast so that it looks like it display 2 digits SSD, but only turn on 1 SSD at a time. I thought that way it could display value 10 but somehow i think I only enable the 2 SSD and have the same value on both. PLease help!
Code: 
module binaryconverter(clk,btn, AN, segA, segB, segC, segD, segE, segF, segG,segDP);
input clk;
input [3:0]btn;
output  reg [3:0]AN;
output   reg segA, segB, segC, segD, segE, segF, segG,segDP;
reg [1:0] data;
reg [24:0] delay;
reg [3:0] digit1, digit2;



always @(posedge clk)begin
if (data == 0)
begin
	AN = 4'b1110;	
	case (digit1)	
4'b0000: {segA, segB, segC, segD, segE, segF, segG, segDP} = 8'b00000010;
4'b0001: {segA, segB, segC, segD, segE, segF, segG, segDP} = 8'b10011111; //single digit
4'b0010: {segA, segB, segC, segD, segE, segF, segG, segDP} = 8'b00100101;
4'b0011: {segA, segB, segC, segD, segE, segF, segG, segDP} = 8'b00001101;
4'b0100: {segA, segB, segC, segD, segE, segF, segG, segDP} = 8'b10011001;
4'b0101: {segA, segB, segC, segD, segE, segF, segG, segDP} = 8'b01001001;
4'b0110: {segA, segB, segC, segD, segE, segF, segG, segDP} = 8'b01000001;
4'b0111: {segA, segB, segC, segD, segE, segF, segG, segDP} = 8'b00011111;
4'b1000: {segA, segB, segC, segD, segE, segF, segG, segDP} = 8'b00000001;
4'b1001: {segA, segB, segC, segD, segE, segF, segG, segDP} = 8'b00001001;
default: {segA, segB, segC, segD, segE, segF, segG, segDP} = 8'b10011111;
	endcase
end
if (data == 1)
begin
AN = 4'b1101;
	case (digit2)
4'b1010: {segA, segB, segC, segD, segE, segF, segG, segDP} = 8'b10011111; //double digits
4'b1011: {segA, segB, segC, segD, segE, segF, segG, segDP} = 8'b10011111;
4'b1100: {segA, segB, segC, segD, segE, segF, segG, segDP} = 8'b10011111;
4'b1101: {segA, segB, segC, segD, segE, segF, segG, segDP} = 8'b10011111;
4'b1110: {segA, segB, segC, segD, segE, segF, segG, segDP} = 8'b10011111;
4'b1111: {segA, segB, segC, segD, segE, segF, segG, segDP} = 8'b10011111;

	endcase
end

if (!delay[17:0])data = data + 1;
if (data >= 2) data = 0 ;
 delay= delay +1;
end
endmodule
 

I don't see, that digit1 or digit2 are set to a value anywhere. Furthermore, the second decoder doesn't cover all input values, keeping the previous output in this case.
 

sorry I quoted the wrong code I wrote before, but I figured it out now! Thank you for your help! :)
 

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