module binaryconverter(clk,btn, AN, segA, segB, segC, segD, segE, segF, segG,segDP);
input clk;
input [3:0]btn;
output reg [3:0]AN;
output reg segA, segB, segC, segD, segE, segF, segG,segDP;
reg [1:0] data;
reg [24:0] delay;
reg [3:0] digit1, digit2;
always @(posedge clk)begin
if (data == 0)
begin
AN = 4'b1110;
case (digit1)
4'b0000: {segA, segB, segC, segD, segE, segF, segG, segDP} = 8'b00000010;
4'b0001: {segA, segB, segC, segD, segE, segF, segG, segDP} = 8'b10011111; //single digit
4'b0010: {segA, segB, segC, segD, segE, segF, segG, segDP} = 8'b00100101;
4'b0011: {segA, segB, segC, segD, segE, segF, segG, segDP} = 8'b00001101;
4'b0100: {segA, segB, segC, segD, segE, segF, segG, segDP} = 8'b10011001;
4'b0101: {segA, segB, segC, segD, segE, segF, segG, segDP} = 8'b01001001;
4'b0110: {segA, segB, segC, segD, segE, segF, segG, segDP} = 8'b01000001;
4'b0111: {segA, segB, segC, segD, segE, segF, segG, segDP} = 8'b00011111;
4'b1000: {segA, segB, segC, segD, segE, segF, segG, segDP} = 8'b00000001;
4'b1001: {segA, segB, segC, segD, segE, segF, segG, segDP} = 8'b00001001;
default: {segA, segB, segC, segD, segE, segF, segG, segDP} = 8'b10011111;
endcase
end
if (data == 1)
begin
AN = 4'b1101;
case (digit2)
4'b1010: {segA, segB, segC, segD, segE, segF, segG, segDP} = 8'b10011111; //double digits
4'b1011: {segA, segB, segC, segD, segE, segF, segG, segDP} = 8'b10011111;
4'b1100: {segA, segB, segC, segD, segE, segF, segG, segDP} = 8'b10011111;
4'b1101: {segA, segB, segC, segD, segE, segF, segG, segDP} = 8'b10011111;
4'b1110: {segA, segB, segC, segD, segE, segF, segG, segDP} = 8'b10011111;
4'b1111: {segA, segB, segC, segD, segE, segF, segG, segDP} = 8'b10011111;
endcase
end
if (!delay[17:0])data = data + 1;
if (data >= 2) data = 0 ;
delay= delay +1;
end
endmodule