The problem isn't conversion of constants, it's choosing an appropriate number representation for your design. Curiously, the application is mentioned only in the post's title.
First, you have to choose a number representation for your filter's data path. I would expect a fixed point signed format, with a specific number of bits left of the decimal point. The coefficients can use an identical or different fixed point format.
The Verilog compiler doesn't know about the fixed point interpretation of signed numbers, it's just an implicite scaling factor. The factor get's important in two places:
- When scaling a multiply result
- When scaling design in- and output signals, and constants
As far as I see, Verilog syntax allows to define the scaling factor and coefficients as real constants and calculate the respective binary representation in the code. I know how to perform this in VHDL, perhaps another forum member can tell you how it works in Verilog. Otherwise, you have to consult the text books. In any case, these are compile time calculations that don't require FPGA resources.