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# binary conversion for filter constants....

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#### pinkyvidya

##### Member level 2
Any one please help me in converting a negative real number having both integer and fractional part into binary and tell me a method to multiply a real constant with a negative fractional number in binary....

For eg:
1: how to convert -3.675 into binary
2: multiply 34 and -0.75 in binary

hi friend,

see this post i think it will help you

see its last program

Thanks...This will help those using matlab.......but i need to represent these numbers as binary in verilog coding......i am implementing one dip functionality in verilog..........kindly reply me

The mantissa and the exponent can have fixed sizes (probably 16 bits for the mantissa and 8 for the exponent). You can´t express these values using less.

thanks......i need to represent those in fixed point format...kindly tell me how to solve the egs: which i have given

Hope this can be of some help **broken link removed**

The problem isn't conversion of constants, it's choosing an appropriate number representation for your design. Curiously, the application is mentioned only in the post's title.

First, you have to choose a number representation for your filter's data path. I would expect a fixed point signed format, with a specific number of bits left of the decimal point. The coefficients can use an identical or different fixed point format.

The Verilog compiler doesn't know about the fixed point interpretation of signed numbers, it's just an implicite scaling factor. The factor get's important in two places:
- When scaling a multiply result
- When scaling design in- and output signals, and constants

As far as I see, Verilog syntax allows to define the scaling factor and coefficients as real constants and calculate the respective binary representation in the code. I know how to perform this in VHDL, perhaps another forum member can tell you how it works in Verilog. Otherwise, you have to consult the text books. In any case, these are compile time calculations that don't require FPGA resources.

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