bidirectional ports using vhdl

[bouvett]

hi i am currently working on a project which involves interfacing an fpga with a glcd. now i need the port that connects the fpga to the glcd datapins to be bi directional. I have already wrote the code:

entity GLCD_BI_DIRECTIONAL_PORT is
    Port ( GLCD_DATA_WRITE : in  STD_LOGIC_VECTOR (3 downto 0);
           GLCD_DATA_READ  : OUT  STD_LOGIC_VECTOR (3 downto 0);
           CONTROL 			: in  STD_LOGIC;
           GLCD_PINS 		: inout  STD_LOGIC_VECTOR (3 downto 0));
end GLCD_BI_DIRECTIONAL_PORT;

architecture Behavioral of GLCD_BI_DIRECTIONAL_PORT is
begin
		PROCESS(CONTROL,GLCD_DATA_WRITE,GLCD_PINS)
		BEGIN
			IF(CONTROL = '0') THEN -- WRITE
				GLCD_PINS <= GLCD_DATA_WRITE;
				ELSE
					GLCD_PINS <= "ZZZZ"; -- SET AS HIGH IMPEDANCE INPUT
					GLCD_DATA_READ <= GLCD_PINS;
			END IF;
	END PROCESS;
end Behavioral;

and it works well when connected on its own, ie itself being the top module. But in my project i need this module to be just one of other submodules and then connect them as a whole in one top level.

When i connect it in a toplevel, i connect the GLCD_PINS shown above, with the top level port, also an inout type using an std_logic_vector.

i do this by writing

glcd <= GLCD_PINS;

now when i write it this way, the system only allows writes from the submodule. when i write

GLCD_PINS <= glcd

the system only allows reads.

What can i do to solve this problem please? I am really confused about this thing :/

thanks for the help.

regards,
Emmanuel Bouvett

 

[TrickyDicky]

connect both at the same time.

Ideally, you should only connect inouts at the top level, and have separate in/out ports internally. Then use input/output enable ports to control the data flow.

 

[amraldo]

Bidirectional IOs can only be connected when they are the top module.
Otherwise, the design wont synthesize.
--
Amr

 

[TrickyDicky]

Yes it will, you'll just get muxes generated.

 

[rca]

I didn't understand your mistake.

entity top is
port (
bidir_port : INOUT STD_LOGIC;
);

architecture A of top is
component sub IS
PORT (
bidir_pin : INOUT STD_LOGIC;
);
END COMPONENT;

BEGIN
i_sub: sub
port map(
bidir_pin => bidir_port;
);

END A;

by this way the bidirectional functionnality is repected.

 

[shitansh]

Yes, rca is correct.