Bias point for class AB power amplifier CMOS in Cadence

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Andriy7

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Hello!

I am designing in Cadence a power amplifier Class AB with output power 20dBm.
Supply voltage is 3.3V, frequency 2.4Ghz, cascode topology, 130nm CMOS .

What is the correct methodology for calculate the DC Bias for class AB amplifier?
 

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