Bias circuit for OTA needed

[wael_wael]

dear friends
i have bias circuit see the figure below, it is feed my ota design (folded cascode) until the current become of ota reach 450 ua, for settling requirement i need 700 ua, could some one help me for this problem(VDD=1.8v_
regards

 

[keoiuser]

you can't increase your transistors parameters so you reach the 700uA?

 

[wael_wael]

thanx, in fact the transistors already very big for example the input of the ota(PMOS transistors) is 270/0.22 um, so it is big value, and for the bias circuit i reduce the size to increase the current of the ota, but i reach the minimum.
regards

 

[wjlzhx]

increase the size of the transistor who conect the res,and reduce the size of the transisiotr byside it or reduce the value of the res

 

[wael_wael]

that right, reducing the resistance is good but has limit, and the transistor conected to res is usualy equale to 4 times other n mos, so i cant play much here
regards

 

[shady205]

Hello Frnd

the W/L ratios are too large....

Firstly see KenMartin Book, which could help u in someway..

For my circuit i need a 100ua for tht circuit it self the W/L ratios are very large and u need to consider the length to be 8 to 10 times of the min length inorder to ignore the Lambda Effect.
So i think i will he hard to design that.. The complete chip area would be the bias it self....



Bhagath

 

[wael_wael]

thank u for ur answer shady, i mean the input transistor of the amplifier by 270/0.27u. so it is not the bias circuit.
it should be big because high gain, high phase margin withe low settling time
regards

 

[shady205]

What is the technology that you are using..?

Even we should consider the Lengths of all the transistors to be 8 to 10 times of the minimun length if it's analog, we can go for the minimum length for digital..

 

[supreet_95]

what is your input bias coming from you bandgap ,feeding your bias block. i believe its too low, because of which you are having to use a huge size and stil not able to get 700ua.


supreet

 

[jeffsky520]

it's difficult to achieve large bias current through this structure , I think, because of limited delta(vgs) and resistance.

 

[shady205]

Then What kind of Bias circuit should be used for high currents...?

 

[supreet_95]

U can generate high currents using current amplification (via mirroring), But it is advisable to do so in 2-3 stages rather than a single stage with large multiplication factor.

 

[shady205]

Hello Supreet..

I had used the Constant Gm bias circuit for 100uA and when mirroring the w/l's were in the range of 500 for a current of 1.6mA.

Is there any good biasing ciruit for insensitive to PVT variations and for high currents...?

 

[guilinwxb]

Hi, shady205:
As far as KenMartin Book, which book ? Can you tell me? thanks!

 

[shady205]

Hello guilinwxb

I had seen better biasing than that of Kenmartins book. It's the modified bias ciruit of kenmartin's .It's not in book it's in some IEEE paper...

When iam designing for 100ua there is a mismatch of about 40-50na and also the sizes of the transistors are large it's about 30. When we need a current of 3mA the sizes should be reflected to the corresponding transistors which would be ( 30 * 30 = 900 ).