clock 9 bi
Hi, probably worthless advice, but I would do it purely digital.
I've got a small 32MC CPLD successfully recovering a biphase coded signal at 12Mhz, in simulation it'll work up to 60Mhz (apparently....)
Its pretty damn simple, and I imgine I'm over simplifying it, since you guys are talking about DPLL's and VCO's. You said you need a stable clock, why don't you just use a crystal oscillator at your receiver, most FPGA's have a built in PLL for running at stupidly high frequencies from lower frequency crystals, and since your signal is 24MHz, it's not difficult to find such a crystal, unless your incoming data slowly changes in frequency, then obviously you would need the DPLL to follow it.
Oversample at about 5-8 times the incoming chiprate and setup an edge detector, with a counter. As I'm sure you know biphase has one or two transitions per 'bit', depending on the data, your counter could just look for for regular transitions.
Anyway, again, sorry if I'm over simplifying this, its just I designed mine from a Xilinx app note, in schematic, took me all but 15 minutes, its quite stable, and not particularly sensitive to jitter, since its running of its own clock (not using the signal itself to clock the entire reciever).
Good Luck
BuriedCode.