Hi arun,
Thank you for your suggestion.however i followed the same thing in my program and getting the result..but the output is coming after 5 clock pulses of the input.
Now i have to solve that..
Can anybody suggest me on this issue..i have to get the output in the next clk pulse.
here i am attaching the code..
For First component:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY bidir IS
PORT(
bidir : INOUT STD_LOGIC_VECTOR (1 DOWNTO 0);
clk,rst : IN STD_LOGIC;
inp : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
outp : OUT STD_LOGIC_VECTOR (1 DOWNTO 0)
);
END bidir;
ARCHITECTURE arch_bidi OF bidir IS
--signal sig_data :std_logic_vector(1 downto 0);
--SIGNAL a : STD_LOGIC_VECTOR (1 DOWNTO 0);
--SIGNAL b : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal oe :std_logic;
BEGIN
PROCESS(clk,rst,oe,bidir)
variable a : STD_LOGIC_VECTOR (1 DOWNTO 0);
variable b : STD_LOGIC_VECTOR (1 DOWNTO 0);
--variable oe :std_logic;
BEGIN
if(rst='1')then
outp<="ZZ";
a:="ZZ";
elsIF clk = '1' AND clk'EVENT THEN
a := inp;
outp <= b;
END IF;
if(a/="ZZ")then
oe<='1';
else
oe<='0';
end if;
IF( oe = '0') THEN
if(a="01" or a="10")then
bidir<= "11";
b := bidir;
ELSIF(A="11" OR A="00")THEN
BIDIR<="00";
B:=BIDIR;
end if;
else
bidir <= a;
b := bidir;
END IF;
END PROCESS;
eND arch_bidi;
Second Component:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY bidir_22 IS
PORT(
bidir_2 : INOUT STD_LOGIC_VECTOR (1 DOWNTO 0);
clk,rst : IN STD_LOGIC;
inp_2 : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
outp_2 : OUT STD_LOGIC_VECTOR (1 DOWNTO 0)
);
END bidir_22;
ARCHITECTURE arch_bidi OF bidir_22 Is
--signal sig_data1 :std_logic_vector( 1 downto 0);
--SIGNAL a1 : STD_LOGIC_VECTOR (1 DOWNTO 0);
--SIGNAL b1 : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal oe_2 :std_logic;
BEGIN
PROCESS(clk,rst,oe_2,bidir_2)
variable a1 : STD_LOGIC_VECTOR (1 DOWNTO 0);
variable b1 : STD_LOGIC_VECTOR (1 DOWNTO 0);
BEGIN
if(rst='1')then
outp_2<="ZZ";
B1 :="ZZ";
a1:="ZZ";
elsIF clk = '1' AND clk'EVENT THEN
a1 := inp_2;
outp_2 <= b1;
END IF;
if(a1/="ZZ")then
oe_2<='0';
else
oe_2<='1';
end if;
IF( oe_2 = '1') THEN
bidir_2 <= a1;
b1 := bidir_2;
elsif(oe_2='0')then
if(a1="01" or a1="10")then
bidir_2 <= "11" ;
b1 := bidir_2;
ELSIF(A1="11" OR A1="00")THEN
BIDIR_2<="00";
B1:=BIDIR_2;
end if;
END IF;
END PROCESS;
END arch_bidi;
Main program after instatiating the upper two components:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY main IS
PORT(
bidir_main1 : INOUT STD_LOGIC_VECTOR (1 DOWNTO 0);
clk,rst : IN STD_LOGIC;
inp_main : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
outp_main : OUT STD_LOGIC_VECTOR (1 DOWNTO 0)
);
END main;
ARCHITECTURE arch_main OF main Is
component bidir is
port(
bidir : INOUT STD_LOGIC_VECTOR (1 DOWNTO 0);
clk,rst : IN STD_LOGIC;
inp : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
outp : OUT STD_LOGIC_VECTOR (1 DOWNTO 0)
);
end component;
component bidir_22 is
PORT(
bidir_2 : INOUT STD_LOGIC_VECTOR (1 DOWNTO 0);
clk,rst : IN STD_LOGIC;
inp_2 : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
outp_2 : OUT STD_LOGIC_VECTOR (1 DOWNTO 0)
);
END component;
signal sig_data1 :std_logic_vector( 1 downto 0);
SIGNAL a2 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL b2 : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal sig_bidir : std_logic_vector(1 downto 0);
signal sig_bidir1 :std_logic_vector(1 downto 0);
BEGIN
u1:bidir port map(
clk =>clk,
rst =>rst,
outp =>sig_data1,
BIDIR =>sig_bidir1,
inp =>inp_main);
u2:bidir_22 port map
(clk=>clk,
rst=>rst,
outp_2=>b2,
BIDIR_2=>sig_bidir,
inp_2=>sig_data1
);
PROCESS(clk,rst,a2,b2)
BEGIN
if(rst='1')then
outp_main<="ZZ";
elsIF (clk = '1' AND clk'EVENT) THEN
a2<= inp_main;
bidir_main1 <=sig_bidir1;
bidir_main1 <= sig_bidir;
outp_main <= b2;
end if;
end process;
end arch_main;
I made enable as internal signal.Here in my program enable depends on the data.