BGR design, need help from experienced designer

[hk2004]

I am working on the trimming bandgap reference design, the target performance is 30ppm.

Some questions need help from experienced designer, thanks so much.

1. Generally fomular for Vref output, Vref= (R2/R1) * (lnN) + VBE. Someone mentioned that adjusting R1 to trimming TC, the reason behind your statement is that, changing R1--> Changing IPTAT-->same as changing IC of VBE--> Changing the VBE TC, am I right?

2. Then trimming the R2 to adjust level of Vref. My quesion is: Can I trim R2 only, both Vref value and TC are trimmed if I adjust the R2 according the Verf= (R2/R1) * (lnN) + VBE. Many open literature reported this method. Actually, trimming R2, both the slope and level are adjusted. I am confusing about the trimming.



3. trimming R1 or R2 or R1+R2 is to trim the bandgap reference first order only. Based on your experience, for CMOS process with parasitic PNP BJT for BGR design, can first order trimming circuit achieve less than 30ppm performace for mass production? Based on the results disclosed in some patents, the curvature(second and third order) triming achieves less than 3ppm improvement compared to first order triming. Over third order curvature trimming is futile for mass production. In industry,does the commercial products desing adopt curvature triming(second even third trimming)? If yes, what's its tempco after curvature trim in mass production?



4. For low power BGR design(total current assumption less than 90uA), how much is the offset of the error amplifier? This offset is need to calcualte trimming range. Is 10mv offset value reasonable?



5. This quesion is related to trimming procedure in mass production. Considering the packaged related mechnical press causes tempco drift, the trimming should be done after chip is packaged. My understanding of the trimming procedure in mass production is listed below. Kindly please comment.

Before the packaged chip is trimmed, I need to know its Vref output curve(If I do not know its cure, How do I trim it, right?). In order to know verf Curve, I have to measure the Vref output at least three temperature point(two extreme temperature plus mid-temp) . After I know the vref curve, if it meet the spec, then no trim. if not meet the spec, I trim it into specified range. But .. . so many measurements need to be done. three times measurement in different temperature for curve, then trim it. Is it accetable for mass production considering the time-cost?

Another quesion is ... If I know the Vref curve, how many temperature points need to be trimmed? two points? (two points defining the slope of the curve)

So many questions, thanks in advanvace.

 

[dick_freebird]

With a two-resistor trim you only need to measure two temps
because you don't have the access to do anything about
curvature.

If you have a "digital" trim then you probably want to test
one temp, running all the codes, then at your final test temp
you run them again and pick the "right answer" (tempco
and output voltage) from all the code combinations, and bang it.

Higher order trimming, by circuit design values, is liable to
be less well controlled (any skew, cubed or worse). Some are
using complex digital table maps, DAC and a temp sensor.
But you'd need a lot more datapoints to fill in that map.

You're almost certain to discover some model fidelity issues,
and getting the bandgap from (say) 50ppm to 20ppm is going
to involve some "black magic" most likely - finding where your
models diverge from real device operation / trends and either
fixing the models (veriloga, if the primitive is just too limited)
or tweaky physical design stuff (one group where I used to
work always laid out the tempco resistors at 45 degrees from
flat, because they got less (or the best somehow) resistor
tempco curvature - bent resistors help the overall tempco
bowing, none).

As to the analytical formulae, they're never more than a
first guess, driving the real assembly to best tolerance is
cut-and-try in the end. I've probably done a dozen bandgaps in
products, and I don't even think about calculating things anymore.
Not much point in it when everything's either a "close enough"
or an outright fiction (reality >> model >> device equation).

 

[hk2004]

Hi Dick_freebird, i quote your comments below.

YOU: With a two-resistor trim you only need to measure two temps
because you don't have the access to do anything about
curvature.

ME: This is the well-known first-order compensation technique. Is this enough to achieve 30ppm performance in mass production ?


YOU : If you have a "digital" trim then you probably want to test
one temp, running all the codes, then at your final test temp
you run them again and pick the "right answer" (tempco
and output voltage) from all the code combinations, and bang it.

ME: Would you please tell more about the "digital" concepts? Since in first-order compensation, the trimming bits(the number of bits depends on the trimming range) may also be called codes. Can you give any documents on your stateoment? thanks so much.

YOU: Higher order trimming, by circuit design values, is liable to
be less well controlled (any skew, cubed or worse). Some are
using complex digital table maps, DAC and a temp sensor.
But you'd need a lot more datapoints to fill in that map.

ME: Would please give more detail description on the higher order trimming for mass production? Can you give some documents described on this?
For my understanding, the performance improvemend achieved by higher-order trimming is very limited compared to first-order compensation. Does it necessary to include higher-order(curvature) trimming circuit ?


YOU: You're almost certain to discover some model fidelity issues,
and getting the bandgap from (say) 50ppm to 20ppm is going
to involve some "black magic" most likely - finding where your
models diverge from real device operation / trends and either
fixing the models (veriloga, if the primitive is just too limited)
or tweaky physical design stuff (one group where I used to
work always laid out the tempco resistors at 45 degrees from
flat, because they got less (or the best somehow) resistor
tempco curvature - bent resistors help the overall tempco
bowing, none).

ME: Thanks for your reminder on the accuracy of the model. I am not very clear about your statement on "45 degree tempco resistors layou" since the layout is genrally placed in inter-digitization with flat form.

YOU : As to the analytical formulae, they're never more than a
first guess, driving the real assembly to best tolerance is
cut-and-try in the end. I've probably done a dozen bandgaps in
products, and I don't even think about calculating things anymore.
Not much point in it when everything's either a "close enough"
or an outright fiction (reality >> model >> device equation).

ME : agree! Cut-and-try need more silicon proven experience. geatly thanks your sharing your knowledge.