Or rather, PLL is not always the safest way to clock logic at a divided clock frequency. Let's say your main clock is 200 MHz. And some stuff needs to run at 50 MHz. Okay, you could use a PLL and divide that 200 MHz by 4, and then use that 50 MHz clock for the low frequency part of the design. Buuuut, the moment you have to pass data between the 50 MHz and the 200 MHz part of the design ... clock domain crossing with all the fun that goes with that. If on the other hand you use a clock enable that is enabled 1 out of 4 cycles, you can keep everything in the 200 MHz clock domain, and still have the slow part run at 50 MHz.