Best way to simulate max. peak current consumed by a circuit block

[tenso]

I am trying to design an LDO and in the process figure out the max current it has to supply (for pass device sizing) and the size of the cap I would need at the output. The LDO is supposed to provide the supply voltage for a previously designed block on my chip. What kind of simulation should I run on my on block (which will be the load ) to figure out Iload max? If I run a transient sim with a ideal voltage source for my block, would that give peak current consumed by the block or would that just give me the quiescent current? If I need peak current at startup, should the DC voltage be ramp voltage with a specific rise time?

How do people decide what the loading profile would like for the current being delivered by a LDO (or even switching regulator)?

--- Updated Sep 10, 2021 ---

I am trying to design an LDO and in the process figure out the max current it has to supply (for pass device sizing) and the size of the cap I would need at the output. The LDO is supposed to provide the supply voltage for a previously designed block on my chip. What kind of simulation should I run on my on block (which will be the load ) to figure out Iload max? If I run a transient sim with a ideal voltage source for my block, would that give peak current consumed by the block or would that just give me the quiescent current? If I need peak current at startup, should the DC voltage be ramp voltage with a specific rise time?

How do people decide what the loading profile would like for the current being delivered by a LDO (or even switching regulator)?

TL;DR
I have an IP block the supply of which is going to be provided by my LDO. I need to find what is max current drawn by this IP block. What kind of simulation would give me this value so that I can size my pass device and decide on a load cap for my LDO?

 

[D.A.(Tony)Stewart]

From your load regulation error spec model it with a voltage source and an equivalent ESR= ΔV/Ipk=Ro

Choose the step load and slew rate you require and from the max ripple error from repetitive step loads from your design spec. Then model a range of caps with known C+ESR. Low ESR ecaps might be ESR*C from 0.5 to 10us depending on family and voltage rating for low power. Std caps 10x to 20x worse typ.

- ceramic caps 10 to 30x better (lower T) until microwave then with NPO are better,
- film caps are similar more or less
- ESL affects SRF and is about 0.5 to 1.5 nH/mm depending on l/w ratio.
- LDO's are unidirectional so do not stop active flyback pulses unless there is a low ESR cap but then if not properly damped with Rs & a flyback diode, it will resonate from Q>0.7