I have never heard of it. It seems to be related to asynchronous design which is not recommended in FPGAs. But it could be at research stage. Delay control in FPGAs is notoriously hard to control and varies from build to build. I assume the main concern on feedback path is that you want to save previous output (without any clocking) until inputs are settled. so how much delay would be implementation dependent and then hard to implement.
nevertheless I have implemented small asynchronous feedback based module in FPGA and controlled delay using extra logic for delay. You can also add timing constraints if tool supports that on logic paths.