GSB
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Hi,
Is there way in system Verilog to compare line by line two files(its not know whether file will have strings or digit so no %s, %d )
Can I call $system in SV to do diff in Questa Sim or Is there any best way to do it like tcl command etc ?
Thanks,
GSB
Is there way in system Verilog to compare line by line two files(its not know whether file will have strings or digit so no %s, %d )
Can I call $system in SV to do diff in Questa Sim or Is there any best way to do it like tcl command etc ?
Thanks,
GSB