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best tool suite for next generation VLSI

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Junior Member level 3
Apr 25, 2002
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hello every one. Now i working for designing next generation VLSI project in china.Can any one tell me the best tool suite for such thing. Now we use synopsys dc for front design. We are going to do about ic place & route .Any suggestion will be apreciated. We want the best tool, for examle,what is good by cadence,what is good by mentor.

what do you mean "next-generation VLSI", what kinda project are you now working on?
I'm in china too, I'd like to know more about your project, would you please tell more here or pm me.


Hi Friends,
What is your next generation VLSI project?
Do you mean next generation process or next generations algorithm?
There are many place and routing tools?
But it depends on your projects type.
If your design is full digital or mixed type, you can use Apolo tools from Cadense.
But your design is analog, you have to use manual type layout tools like Opus from Cadense.
Cadense tool is more popular between place and routing engineer.
Drawing is not so much important.
The most important thing is verifying your layout design.
Are you consider about it?
We call DRC and LVS.
If you use back-end design house, you need not consider about them.
But if you have to layout by your self, you should handle DRC and LVS rules.
It is not easy to stater.
Be careful about verifying.
I hope you project is going well.
Thank you.

Much thanks for kunjalan.For some reason I am sorry I can't tell more clearly for my project. I can only say this is about 0.1um level design . But if someone have experirence in design for 0.1um pls let me know. I now just have two question :
1.delay model in 0.1um.Is the model much different from 0.25um. 0.25um we use asic vendor place&route 0.1um we just want to do by 3td party tools so we can change vendor later.Pls introduce some .

Why don`t you ask Candence or Mentor in china to help you? An introduction about place and route tools is what they want to do, and you can ask them the same questions you mentioned here. I think "0.1um" is a huge project and cost is high(at least the mask cost is not cheap). Just my persional opinion.

Yes. We also will let company sales manager to introduce their products.But they are salers not engineers.And i think this place will be more open and accurate by yours friend.

Hi all
mysuggestion is as for unix cadence is best because its seamless ,for windows model sim microcap dolphin and others.

Hello! 0.1um is very advance project. I can't image what kind of project will use it unless CPU,FPGA,chip set and memory. In this kind of process, 0.2 um Al wire will be to thin (high resistence) and space too short (high coupling capacitance). I think Cu metal wire and Low-K (> 3.9) will be used. So place and route should be careful.

For digital back-end I suggest SoC Encounter. I myslef had a good experience on this tool lately.

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