For system like delta sigma ADC the simulation of the whole system in circuit level directly will consume many days so we need to first to design a simple behavirol model for entire delta sigma ADC before map this case to circuit level to minimize the time consumed for your design.
you can do this using Matlab or verilog-a , verilog-AMs and both also subitted in cadence ,ADS tool also available.
for example for delta sigma ADc the most available tools in matlab
for PLL design you can find verilog models and matlab ones also.