beginner verilog question

[donvaun]

is it possible to call a function using the case statement?

something like:
always @(a) begin
case (a)
one: "module name"
'
'


if not, how can i create somthing similar with this?

 

[hareshcooleng]

ya its possible to call function with case statement
always @(selection, input)
case(sel)
try it

 

[donvaun]

ya its possible to call function with case statement
always @(selection, input)
case(sel)
try it

thnx.. so how do i do with the syntx.. i tried doing it this waybut seems got error:
always @ (sel, a)
case (sel)
sel: = m m(.clk(cin), .a(a), .b(b), .p);


is this correct?

 

[permute]

a module isn't a function.

a function is something that can be done within 1 cycle, using one or more inputs, and providing one output.
a module has inputs and outputs and defines the logic and structure used to implement the logic.

most likely, you want to instantiate the module outside of the always block, then use logic to select the correct inputs/outputs from the module.