Hi Welton
For investigating latch-up there are 2 standardized tests used throughout the industry: Both tests are described in the JEDEC78A document, available from the Jedec website:
https://www.jedec.org/download/search/jesd78A.pdf
1. Bias the chip like during normal function. Add pulse on top of the supply potential. Parasitic devices or ESD protection elements might get triggered by this pulse leading to latch-up situation. Typically the IC should be able to sustain 1.5xVdd without latch-up. This level might be increased for IC's with inductive connections
2. Bias the chip like before but this time inject current pulse into the IO's. Typically a level of 100mA must be tolerated without latch-up. For harsh (automotive, industrial) environments levels of 300mA are used.
Results for both tests should be displayed on the datasheet of the IC vendor.
Watch-out: Most latch-up problems are worse at elevated temperature.
Besides those standardized tests there are some other test conditions that strongly vary per application or IC/OEM company. E.g. it is typical in the LCD panel drivers to apply so-called 'CCL' - Charged Capacitor Latch-up tests. This basically is similar to applying a Machine Model (MM) Electrostratic Discharge (ESD) stress, while the IC is biased. Other names for similar tests are V-latch, AC-latch-up. In some other industries, OEM's may use a so-called 'ESD ZAP-GUN' to apply system level ESD stress at the finalised system during operation. Information about these test types are only seldom mentioned on datasheets since these are not standardized tests.
Maybe this is what happened to 2 out of the 10 chips tested: Maybe these 2 chips received an ESD stress during the long operation tests. This is possible when there was human or machine interaction closeby the test setup during the tests.
For solving your problem...
- Do you have an idea about the failure location. Is it possible for you to perform physical failure analysis? Maybe the IC vendor might provide help here.
- Do you have an idea about the ESD protection approach used in the IC?
- Is it possible to stabilize the supply potential by adding a large capacitance (uF) across Vdd-Vss of the IC?