Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Basic questions regarding CPLD

Status
Not open for further replies.

pup

Newbie level 4
Joined
Nov 8, 2004
Messages
7
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
51
CPLD for me?

I m only a begineer and would like to know some about cpld.

1.Which prerequisite are required to learn PLD family?
2.Is it true that CPLD resouces are less than that of FPGA?Why?
3.Please give me some guide line or some books or links to learn .
 

CPLD for me?

Salam,

"Digital Design with CPLD Applications and VHDL" Ebbok



"Introduction to CPLD and FPGA Design"



Look also to


Bye
 

    pup

    Points: 2
    Helpful Answer Positive Rating
Re: CPLD for me?

The limitation on CPLD resourcs is based on its structure, it is SOP based.
 

    pup

    Points: 2
    Helpful Answer Positive Rating
CPLD for me?

CPLD is very easy to learn for begineer. Its structure is simple, but you can understand completely its design method and development flow.
It is time for doing sth.
 

Re: CPLD for me?

I'm also beginner .
i don't know what SOP stands for?
Can you give me some more explanation ?
 

    pup

    Points: 2
    Helpful Answer Positive Rating
CPLD for me?

Salam,

SOP = Sum Of product.

You can implement any logic circuit by draw it's truth table then from the truth table you can find equation for the o/p using AND & OR gates only.
CPLD uses these tech. It uses programmable AND & OR Gates array.
Note: this in simple, but actually it the Logic Cell contain Flip-Flops and MUX for handle all logic modes.

But FPGA architecture based on LUT (Look Up Table) , the number of i/p to LUT is 4 and the o/p is 1

so you can directly transfer a 4*1 truth table without using programmble AND or OR array gates.
Buy using many of LUTs units you can implement any complex logic desgin.
You Can use LUT as 16*1 RAM Block.

Bye
 

    pup

    Points: 2
    Helpful Answer Positive Rating
Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top