Basic question about DAC interfacing

[hithesh123]

In a SPI interface DAC with sampline rate 100KSps, like the DAC7654.

How often should the data be written to the DAC from a uC.
The SPI speed is usually in MHz.
Do you write data, at say 1MHz.
Do you have to wait for the DAC to read out all the bytes or can you just keep writing?

 

[crutschow]

You write the data as fast as you want the DAC data to change value.

Whether you have to wait depends upon the protocol of the SPI bus.

 

[hithesh123]

You write the data as fast as you want the DAC data to change value.

Whether you have to wait depends upon the protocol of the SPI bus.

ok, so the DAC has enough registers to buffer the written data.
When the datasheet says 100Kps, my understanding is the DAC needs 100k digital values written in 1sec. Is that right?

 

[crutschow]

............................
When the datasheet says 100Kps, my understanding is the DAC needs 100k digital values written in 1sec. Is that right?

Where did you see the value of 100Kps in the data sheet? The Figure 4 timing table shows a minimum clock high and low time of 25ns each which would give a maximum clock frequency of 1/50ns or 20MHz with each DAC requiring 24 bits to update. This means each of the 4 DACs requires 24 * 50ns = 1.2µs to update or 4.8µs to update all four.

That's the maximum update rate you can use but you can go as slowly as you like. There is no minimum update rate. The DAC output will just stay at its previous value until updated.

 

[hithesh123]

Where did you see the vale of 100Kps in the data sheet? The Figure 4 timing table shows a minimum clock high and low time of 25ns each which would give a maximum clock frequency of 1/50ns or 20MHz with each DAC requiring 24 bits to update. This means each of the 4 DACs requires 24 * 50ns = 1.2µs to update or 4.8µs to update all four.

That's the maximum update rate you can use but you can go as slowly as you like. There is no minimum update rate. The DAC output will just stay at its previous value until updated.

Sorry I didn't see the 100KSps in the datasheet. I saw it on digikey page - https://www.digikey.com/product-detail/en/DAC7654YT/296-28746-2-ND/1509203

How do you find the Bandwidth of the DAC.

The SPI writing speed depends on the desired freq of the Analog output signal. right?
If I want a 1KHz sine wave. The SPI data has to be updated at 1KHz speed?

 

[crutschow]

Sorry I didn't see the 100KSps in the datasheet. I saw it on digikey page - https://www.digikey.com/product-detail/en/DAC7654YT/296-28746-2-ND/1509203

How do you find the Bandwidth of the DAC.

The SPI writing speed depends on the desired freq of the Analog output signal. right?
If I want a 1KHz sine wave. The SPI data has to be updated at 1KHz speed?

The timing characteristics of the digital signal are given in Figure 4 of the spec sheet, as I stated. That gives you the maximum digital update speed. The analog output requires 12µs to settle so that puts an upper limit on updating each DAC at 83kHz.

The writing speed to output a 1kHz sine wave depends upon how many samples you use to generate the sine wave. Each output sample of the DAC is one voltage point of the sine wave. So you would multiply the number of points you need to generate the sine-wave times 1kHz to get the DAC update speed.

Do you understand sampling theory? In theory a single-frequency sine wave requires at least two samples to reproduce the sine wave but in practical cases, many more samples than that are used. It depends upon the analog filter used as part of the reconstruction of the sine wave from the samples and how accurate a sine wave you need. The 83kHz settling time means that the maximum number of samples you can generate per each cycle of the 1kHz sine wave would be 83.