min2209
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Hi all,
I've been trying to design a CMOS op amp using Cadence to achieve 45 degrees phase margin and a gain of 1500 Vout / Vin at 100KHz. The circuit is as follows:
This circuit achieves the appropriate amplification, but to find out whether or not it satisfies the phase margin requirement, I need to find the loop gain of the feedback path. I've been trying to use the iprobe element in the analoglib, but it hasn't been giving me useful results (it says the phase margin and gain both start at <0).
Does anyone have any ideas?
Thanks!!!
Min
I've been trying to design a CMOS op amp using Cadence to achieve 45 degrees phase margin and a gain of 1500 Vout / Vin at 100KHz. The circuit is as follows:
This circuit achieves the appropriate amplification, but to find out whether or not it satisfies the phase margin requirement, I need to find the loop gain of the feedback path. I've been trying to use the iprobe element in the analoglib, but it hasn't been giving me useful results (it says the phase margin and gain both start at <0).
Does anyone have any ideas?
Thanks!!!
Min