Is reset recovery time with respect to assertion of the reset and reset removal time is with respect to reset removal time? Is there any good document which says basics about reset recovery and removal time?
But here they defines this timing with respect to the inactive edge of the reset and with respect to the falling edge of the clock. Is that this is the way these timings are defined? Are not they defined with respect to active edge of reset and rising edge of clock?
But the document in solvnet writes closing edge. How can a closing edge be rising edge? Closing edge should be falling edge for a positive logic digital system.