entity sync is
generic (
RESET_STATE : std_logic := '0' -- '0' for active low sync
);
port (
clk : in std_logic;
rstN : in std_logic;
d : in std_logic;
q : out std_logic
);
end entity;
-- ----------------------------------------------------------------
architecture behavioral of sync is
signal d_meta : std_logic;
begin
process(clk, rstN)
begin
if (rstN = '0') then
d_meta <= RESET_STATE;
q <= RESET_STATE;
elsif (clk'event and clk = '1') then
d_meta <= d;
q <= d_meta;
end if;
end process;
end architecture;