phased
Newbie level 2
I'm having some confusion regarding a design: I have a 20 MHz clock on my system that connects a CPLD. The CPLD's only purpose is to act as an 'intelligent' shift register with an SPI interface - it also has a parallel input. I designed the system in such a way that it sampled SCK on every rising edge of the clock and synchronized SCK with the clock as, from what I've learned, asynchronous design in CPLDs/FPGAs is a no-no.
The trouble with my design is that it works fine at 1 MHz but at 2 MHz it transfers bad data occasionally. I believe the issue is that my MISO waveform is nearing the tolerance of the setup time for the SPI interface in my MCU (which is the master). You can see that here:
The obvious solution is to utilize a faster clock (40 MHz as opposed to 20 Mhz) but I was hoping there was a better way. One approach that I thought of was instead of using the clock, I should directly use SCK to output data. Here's another that shows more clearly how close I get to the setup time:
I only have a 50 Mhz o-scope, but I also looked at the 20 Mhz clock and SCK. The 20 Mhz produced, as expected, about 10 cycles during one cycle of SCK. Because of the synchronization and edge detection of SCK, I'm writing data to MISO about three clock cycles later than the actual falling edge of SCK. So, my question is, is there a better way to design this?
The trouble with my design is that it works fine at 1 MHz but at 2 MHz it transfers bad data occasionally. I believe the issue is that my MISO waveform is nearing the tolerance of the setup time for the SPI interface in my MCU (which is the master). You can see that here:
The obvious solution is to utilize a faster clock (40 MHz as opposed to 20 Mhz) but I was hoping there was a better way. One approach that I thought of was instead of using the clock, I should directly use SCK to output data. Here's another that shows more clearly how close I get to the setup time:
I only have a 50 Mhz o-scope, but I also looked at the 20 Mhz clock and SCK. The 20 Mhz produced, as expected, about 10 cycles during one cycle of SCK. Because of the synchronization and edge detection of SCK, I'm writing data to MISO about three clock cycles later than the actual falling edge of SCK. So, my question is, is there a better way to design this?