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Bank of 2nd order IIRs connected sequentially on FPGA

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Unomano

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I'm a newbie with FPGA and looking for some help in my project.
I have a signal which is a number of pulses of 100 kHz sine sampled at
1 MHz. The problem is that it is shadowed in a number (up to 10) of
interfering continues wave signals at frequencies in 50-200 kHz band,
and I want to suppress them. I decided to use a bank of 2nd order IIR
notch filters connected sequentially. The filters considered to be
adaptive, because the frequencies of interfering signals are unknown.
I decided to build the project on TMS320F2812 DSP and Spartan 2 FPGA
connected to DSP via memory interface. I have difficulties with
choosing the IIR filter structure, arithmetic distribution algorithm,
and don't know what domain better fits my task (VHDL, Verilog or
schematic). Could you please suggest me some considerations on the
problem.
 

FrankCh

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Verilog is best due to simpler learning curve.
Plus there are more help in Verilog than VHDL.

Plus, with IIR you had better stay in DSP processor since in FPGA, bit-width is
fixed and IIR is a route to overflow.
 

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