Hi,
If I see this right, then you gain to use only one inductance instead of two.
But you need three switches instead of two
And the rest is the same.
A drawback is, that the inductance current must be zero before you start the next cycle.
***
To your single question:
The control loop bandwidth needs to be smaller than the switching frequency.
You said: "the design works well" ... so you should know this already.
The max. control loop run frequency is the PWM frequency. So the ADC frequency should be the same as the control loop frequency
If so, then accirding nyquist the bandwidth is limited at half of the sampling frequency.
I'd choose the control loop bandwidth on
* output capacitor
* max load current (both give the max negative slew rateof the output voltage)
* then you need to decide max expected deviation (this gives the reaction time you need)
Klaus