Bandgap with 60dB of PSRR at 1MHz

[PSG]

Hi,
I'm trying to design a bandgap with a pretty high PSRR at high frequency (for a switching regulator which frequency can go up to 1Mhz). I've tried a pre-regulation, I've tried voltage subtraction, but the best I get is 30dB at 1MHz.
Any ideas on what architectures would work best for this design? Also I'm limited to 10uA of currents. Is this feasible?
Thanks.

 

[dick_freebird]

Might try a pre-regulation that does not involve an
op amp / closed loop scheme. For example I have
had excellent results from a stack of MOS-diodes as
a reference and a source follower producing a ~3V
crude supply. Tempco is poor but the thing responds
very little to VDD perturbations, even at fairly high
frequencies (I am using it in >1MHz buck converter
chips).

At 10uA overall, you won't have much to spare but
a few small MOS-diodes cost little, and big capacitor
& pass-FET cost no current.

 

[PSG]

Thanks for the idea dick_freebird but I need a low tempco reference (bandgap style) for my LDOs and ADCs, I can't just use 3 MOS diodes as reference. Process variation I can live with since I'll trim it.

Anyone else has some idea?

 

[dick_freebird]

I mean, use that sort of simple / decent HFPSRR "LDO" as
the preregulator for the bandgap, not the prime reference
itself.

I also hung the error amp and timing ramp off the
same internal supply. Got line rejection through the
whole chip, of less than 1mV from 3.5 to 6V in. The
<1mV being a DMM resolution limit on the bench.

 

[saro_k_82]

I have achieved this by operating the bandgap within a sub-regulated bias loop. I designed my own architecture for the concept but there are a few ieee papers about this. I obtained 120dB psrr at dc.