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Bandgap supply rejection

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benchen

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When I was simulating the bandgap, I found the PSRR is hard to be good when the Vcc is at different level.

The best PSRR appears when the Vcc is round 3.0v, above 90db.but deteriorate rapidly when Vcc deviates 3.0v. When Vcc=3.6 is about 40db, and when Vcc=2.7, the PSRR is also poor. I replaced the amplifier and Start up circuit to ideal one, the same thing happend. I wonder why should this happen? What factor is the dominating one to affect PSRR in this bandgap circuit? And how to improve it?

The core part of the bandgap schematic is in the attachment file.
 

liuyonggen_1

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benchen said:
When I was simulating the bandgap, I found the PSRR is hard to be good when the Vcc is at different level.

The best PSRR appears when the Vcc is round 3.0v, above 90db.but deteriorate rapidly when Vcc deviates 3.0v. When Vcc=3.6 is about 40db, and when Vcc=2.7, the PSRR is also poor. I replaced the amplifier and Start up circuit to ideal one, the same thing happend. I wonder why should this happen? What factor is the dominating one to affect PSRR in this bandgap circuit? And how to improve it?

The core part of the bandgap schematic is in the attachment file.

in my opinion,vbe will be changed greatly as the supply decrease to some point ,which result in the decrease of the output greatly. i suggest you test the voltage between the base and the emitter of the bottom transistor
 

jwfan

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Perhaps you should check the operation region of the transistors in different supply voltage.
 

fnlee

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adding cascode devices will reduce the supply voltage sensitivity of the Vref.
 

rfsystem

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I think that the amp in the middle of the schematic have limited supply rejection. You can test that if you sweep the supply from your min to max VDD spec and plot the amp diff input voltage. I think at the VDD where PSRR is best the diff input voltage is zero.

A encounter similar effects long time ago. I use a bias for the amp which is derived from the bandgap cell. But the startup gets more difficult then.
 

xerxer

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i met the puzzle as you . maybe your transistor is in wrong work region when vcc is higher or lower than your normal vcc . check your current and transistor region .
when current is too large or small your transistor may work in work region .
 

J

jiangwp

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Maybe, the amplifer parmeters have to verify when the power supply is higher or lower than the typical condtion.

Just as:
the input common mode range
the output swing

other thing is your sweeping speed about the power supply.
Maybe, the amplifer bandwidth is not so large, so its output can not follow the power supply varing , so the upper mirror can not work normally.

and the psrr about the amplifier does effect to the bandgap too.
 

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