IADanilov said:It is ~ 1.2 V typical reference voltage for conventional Bandgap. Try to adjust your circuit to reach this value.
In other words, you should get good Vref vs. Temp characteristic. Typically it obtained at ~1.2 V value of Vref for conventional Bandgap.
dick_freebird said:We can't see any sizing information, but presuming
all are "1X", your "diode" (SPNP) ratio of 2:1 is way
low for decent signal to the "op amp". Circled.
dick_freebird said:Making the output a mirror-fed, independent stack
gives you a degree of freedom but produces no
load-regulation ability at all. OK for capacitors but
not anything that needs DC load range. You can
perhaps modify that stack ({) for a different tempco
than the "core" by varying diode ratio and resistor
value; I'd try and get the core stabilized first, then
"shotgun" some sizings in the output stack to see
what you can get.
It's useless information because on attached schematic there are no any elements' names.The size of the transistors
A piece of advise to you is to plot the DC analysis graph for temperature.aredhel_vlsi said:well I've tried different values of R2( the left one)
- for R2=18kΩ the error is 0.45% which is satisfying I think but the transient analysis is 1.092 Volt for Vref. it is given first graph.
-for R2=18.5kΩ the error is 0.6% and Vref = 1.099 Volt
-for R2=19kΩ the error is 0.8% , Vref =1.106 volt
as the resistance increases the Vref is better but the Temp graph is getting worse which is natural, but what could I do to compensate that?
what is the % limit error to accept the temp analysis as satisfying one? Is it too wrong to get a 1 Volt V reference?
the graphs are following.
thank you for your support
aredhel_vlsi said:Ηi, could somebody tell me how I can get a plot with derivation θVbe/θT using calculator?
Ι have a Vbe graph like the following.. how will I make the deriv expression? I've tried something but it shows the message that it can't be plotted.
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