Looks like you are trying to build a 1.2V reference., other architecture would have given you a better o/p impedance straightaway. With this circuit, you need to add a buffer to reduce the o/p impedance.
If you take any OTA from your circuit, just put feedback around it and you have low impedance at the output. In that way you buffer the voltage level lowering the impedance
Yes it is a common drain stage with feedback. As it uses an NMOS transistor one has to check for voltage compliance. As the op-amp should produce a positive signal (wrt to output) to drive the NMOS. I think it can be done with a PMOS transistor too, you should check out some LDO topologies.