Band gap voltage reference 40nm remove the Vdd dependency in all cornners

[Dino1400]

I'm designing a BGR 40nm for 0.9-1.35V my simulation shows that Vref is depend slightly on Vdd (100mV slope) i have made all the transistor saturated for all corners however is still depends on VDD any suggestions.


Thank you al in advance

 

[erikl]

Re: Band gap voltage reference 40nm remove the Vdd dependency in all corners

... i have made all the transistor saturated for all corners however is still depends on VDD .

Probably depends on your design (which you didn't show). Can you use a preregulator (LDO) for 0.9V ?

 

[dick_freebird]

This is sub-bandgap territory, folded I expect and still every
current source or mirror that matters, will be swung from
linear to saturation across that range if you are driving
into a diode (you are, somewhere). Current mirror fidelity
I imagine is the main problem. I think you need to look at
stuff like replica feedback for current bias master (feedback
current taken by an amplifier that matches the (vdd-Vf)
headroom. But I'd still also expect a gross change in any
poor-boy bias network (like resistor bias into a simple
mirror, your vdd-VT number will swing way wide). You may
consider making a better controlled reference current
generator to bias the main bandgap (you may self-bias
or you may find that independent chaining gives less
potential for weirdness).

You ought to spend some time figuring out how vdd gets
into what, that makes the DC PSRR so poor. And given
that it is so poor at DC, is there a frequency range where
your PSRR becomes over-unity amplification of supply
activity?