Hi,
You show boxes, not Mosfets. The datasheet of the FDD4141 shows Mosfets and the body diodes they have in them. Their connections are not shown as 123 like you show.
Very witty, I don't like the yellow box Spice model, either, no idea why they didn't use a standard PMOS shape. You mean I wrote K---A backwards with the vertical FETs... My mistake.
Here is an FDD4141 description and simulation pertinent to your remark. I use it the right way round, there was no definition of Spice model pins so in 2017 I had to do an identical circuit to identify source and drain.
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Hi,
Added cleaned-up/simpified schematic of circuit. Is there any reason this circuit can't work:
With no resistor at node B, pairs 1a and 1b should be on and pair 2 should be off.
With a resistive load at node B, pairs 1a and 1b should be off and pair 2 should be on.
In simulations, it oscillates/chatters on and off before the resistive load is connected via the timed switch.
In DC value analysis, with no load there is >3.5V at node B and with any load (1G down to 1R) there is an operatiing point error message at node C1.
Pull-down resistors at each floating node don't solve the issue, and mess-up the expected 2.662V + op amp offsets (around 12mV in total at the comparator input).
Lastly, any reason images called e.g. DSC_1234 don't upload on the forum?
Thanks