back-end adc in pipelined adc

[ljy4468]

hi all~
I'm designing 12b 80M pipeline ad
and there are lots of problems........

I want a question about B.E. a/d.
i use 1.5bit resolution per stage.
and B.E. ad is 2bit flash a/d

And Can i use 3bit flash or 4bit flash AD in back-end???
If so, what's the drawback??

and if i made a 4bit pipeline,(1stage(1.5bit) + 3bit flash)
output will
00 <-first stage digital output
+ 000 <-3bit flash output code
-----------
0000 <-final output

is it right???

 

[analoger]

I think you are right, but you have to design a 3bits flash adc, and you also have to design the comparators which are more stringent .

 

[tuza2000]

why not 1.5+1.5+2？ i think it is better!
regards

 

[ljy4468]

THNKS TO YOUR opnions.
but, tuza2000,
why is 1.5+1.5+2 is better?
please tell me why.

thanks

 

[sunking]

in idea, you can design any bits flash adc.
But it is trade of power, speed, bits and so on.
maybe the simplest is 1.5bits every stage.

 

[tuza2000]

ljy4468:I think the digital correction is better.
and 1.5bit/stage is the simplest.

regards