[SOLVED] AXI4-Lite Read Error

[aquanaut]

Hi All,

I'm using Xilinx's 1G and 10G Ethernet IP core which has AXI4-Lite interface for register access. I'm using only one AXI interface to access both the cores.

When I read 1G registers it reads correctly but when I try to read 10G registers it gives SLVERR, that is rresp="10". I have attached screenshot here. Please look at it.

Thanks in advance...

 

[ads-ee]

What is up with your clk_50m's duty cycle? It looks like you generated it the logic fabric instead of using a PLL/MMCM.

Besides the protocol of the signals you showed, which look okay to me. I couldn't say what is wrong since this screen capture just shows that the slave received an address and is producing a response of 2'b10.

Perhaps you should spend time debugging the design. You probably hooked the 10G AXI up incorrectly.

Regards

 

[aquanaut]

Hi ass-ee,

Thanks for your reply...

These signals are capture from hardware through ILA debug core, like chipscope. So because of sampling frequency, it doesn't show correct duty cycle otherwise I have generated this clock from MMCM only.

The interesting thing is, the same interface works with Tri-MAC core's AXI interface. It reads the register successfully. The core connections are also ok because it transfers data correctly. Only the problem is with AXI interface of 10G MAC core.

Thanks

 

[aquanaut]

Hi,

I found the solution of this problem. There was an issue with MAC core reset. The core was staying in reset due to which it was returning SLVERR in response. It was working with Tri-MAC because the reset is different for it than 10G MAC.

Thanks