[SOLVED] AXI4 full read burst over AXI4 interconnect to DDR3 controller IP

[dpaul]

Hello,

I am using the Microchip Libero SoC tool. A part of my design consists of an AXI4 Master, AXI4 interconnect IP core and the DDR3 Controller IP core.

The AXI4 master issues burst read requests to the DDR3 controller via the interconnect. Burst length is 8, burst type is INCR and burst size is 4. My read data bus width is 128 bits. So when I place a read request starting from address 0x8000_0000, I get data in the form of 8 beats from location 0x8000_0000 to 0x8000_007F. So far all good.

But if I place a read burst request starting from location 0x8000_0018, I get the burst data starting from location 0x8000_0010 to 0x8000_008F. That is the LSByte of the 1st beat in the read data does not correspond to the data for location 0x8000_0018. Why does the reading not start from 0x8000_0018?
My understanding was that for the 1st beat of the burst, the data would be from loc 0x8000_0018 to 0x8000_0027, then from loc 0x8000_0028 to 0x8000_0037 , and so on for the remaining 6 beats of the burst read. But this is not so, any ideas why?

This behavior tell me that the starting address of any burst must be aligned to 128 bits boundary (i.e. aligned to the read data bus width here). Can anyone confirm this?

I have checked the AXI4 interface signals of the DDR3 controller and see that the start of the burst address has be properly forwarded by the AXI interconnect IP.

Regards.

 

[TrickyDicky]

This wil be because you set ARSIZE (burst size) to 4. This indicates that each transaction on the bus is 16 bytes wide. Can I also assume the interface is 128 bits? It is usually easiest to set the ARSIZE value to match the bus width, otherwise you have to do "narrow" transfers (see A3.4.3 from the AXI4 spec).

The RDATA channel has no byte enables, so effectively any address specified to no align to the ARSIZE value will return the full word anyway, effectively ignoring your MSBs of the address because it is always word aligned. It is up to the receiver to know which bytes they requested when the address offset does not match the word boundary.

Your problem has en example in the AXI spec, Figure A3-13 - Aligned and Unaligned Transfers

 

[dpaul]

Thanks for the fig numbers from the spec and confirming my understanding.

Can I also assume the interface is 128 bits?
Yes. Both the master and slaves have 128b i/f with the interconnect.

It now seems then to properly handle those data from the burst, I either need to do a narrow transfer by changing ARSIZE to 3 (I do not want to change the i/f size) or have arrays inside my module with a size and depth that will save data of the complete burst and help me in processing them effectively.