AXI master and slave with different clocks

[sun_ray]

Suppose an AXI master is working with a completely different clock than the corresponding AXI slave. Can there be scenarios when ARADDR, RDARA, AWADDR, WDATA needs also to be synchronized?

 

[sharath666]

What do you mean by different clocks? Shouldn't the slave work on the clock provided to it by the master?

 

[sun_ray]

sharath666 or anybody

Is it that slave will have to work with the same clock provided by the master in the above case at post number 1? Is it that the AXI master cannot have a different clock than the AXI slave in the above case as in post number 2 ?

Please provide a solution for post number 1 if an AXI master can have a different clock than the AXI slave.

Regards

 

[layowblue]

Hi Sun_ray, in your duplicated post I've copied AXI protocol part. Anyway, I'll paste it here again:
AMBA AXI Protocol excerpt:

"ACLK Clock source Global clock signal. All signals are sampled on the rising edge of the global clock."

 

[sun_ray]

Hi Sun_ray, in your duplicated post I've copied AXI protocol part. Anyway, I'll paste it here again:
AMBA AXI Protocol excerpt:

"ACLK Clock source Global clock signal. All signals are sampled on the rising edge of the global clock."

But suppose a master with AXI interface wants to operate at a faster frequency than the corresponding AXI slave with which the master is interacting. Do you want to mean that that cannot be done? Do you want to mean that the AXI master and AXI slave will have to have the same clock?

 

[layowblue]

"Global clock" literally is self-explanatory, unless you have two globes(Mars?)

 

[xtcx]

Still the clock will be same, but the slaves will run through wait-states or step-down version of the same clock, for eg., Master @ 100M and slave @10M, hence still rising edge applies to all slaves.

 

[sun_ray]

Still the clock will be same, but the slaves will run through wait-states or step-down version of the same clock, for eg., Master @ 100M and slave @10M, hence still rising edge applies to all slaves.

xtcx or anybody

Do you also want to mean that clock cannot be different for an AXI master and the corresponding AXI slave?

 

[ivb1991]

Of course AXI master and slave can operate on different clocks(with different frequencies and/or phases). Such situation is common in large designs like SoC, and called "clock domain crossing"(CDC). In case of AXI it's necessary to implement AXI2AXI asynchronous bridge.

 

[imbichie]

Hi Sun_ray,

Did you mean like this :
For example, if we have an AXI master say DMA, and an AXI Slave say DDR_Mem_Controller (DMC).
So in actual case both the master DMA and the slave DMC should be working in the same frequency (Global clock ACLK).
But the slave DMC can read/write data to the DDR Memory (which is controlled by the DMC) in any other clock (depends upon the DDR memory clock).
Means as per the communication between the AXI master DMA and the AXI slave DMC whould be in the same clock,
but after the communication the slave can drive those data to the DDR memory with any other clock.

note: As per my knowledge the AXI Slave , AXI Master and the AXI Bridge should be in same clock ACLK

 

[ivb1991]

Hi Sun_ray,
note: As per my knowledge the AXI Slave , AXI Master and the AXI Bridge should be in same clock ACLK

Wrong. It's not forbidden to set different clocks for master and slave.

 

[imbichie]

Hi ivb1991,

As per the AMBA® AXI Protocol v1.0 Specification

11.1.1 Clock
Each AXI component uses [B][COLOR="#FF0000"]a single[/COLOR][/B] clock signal, ACLK. All input signals are sampled
on the rising edge of ACLK. All output signal changes must occur after the rising edge
of ACLK.

So in the AXI system (AXI Masters, AXI Slaves and the AXI Bridge) uses the single clock, ACLK for the transaction.

inside the AXI master and/or AXI slaves, there can be multiple clock domains, but the AXI transaction should use the single clock ACLK

 

[sun_ray]

Hi Sun_ray,

Did you mean like this :
For example, if we have an AXI master say DMA, and an AXI Slave say DDR_Mem_Controller (DMC).
So in actual case both the master DMA and the slave DMC should be working in the same frequency (Global clock ACLK).
But the slave DMC can read/write data to the DDR Memory (which is controlled by the DMC) in any other clock (depends upon the DDR memory clock).
Means as per the communication between the AXI master DMA and the AXI slave DMC whould be in the same clock,
but after the communication the slave can drive those data to the DDR memory with any other clock.

note: As per my knowledge the AXI Slave , AXI Master and the AXI Bridge should be in same clock ACLK

I am only mentioning now AXI master say DMA, and an AXI Slave say DDR_Mem_Controller (DMC). I am not mentioning in this thread DMC can read/write data to the DDR Memory. Please inform if it is not clear.

- - - Updated - - -

Wrong. It's not forbidden to set different clocks for master and slave.

Can you please provide a solution as asked in post number 1 then if different clocks can be provided to the master and the slave?

 

[ivb1991]

sun_ray, example of async AXI bridge from ARM(pdf download is available): http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dto0023b/index.html

 

[sun_ray]

Is it possible to send as an attachment?

 

[imbichie]

Hi sun_ray,

in the AXI system (AXI Masters, AXI Slaves and the AXI Bridge) uses the single clock, ACLK for the transaction.

inside the AXI master and/or AXI slaves, there can be multiple clock domains, but the AXI transaction should use the single clock ACLK

So we cant have different clocks in AXI Master and AXI Slave if its connected to a Common AXI bridge.
If its a single AXI master and Single AXI slave, then it may be possible to do the transaction by providing appropriate CDC schemes.
But logically its difficult, because the all the VALID and READY and LAST signals should be valid in a single clock pulse,
so if the master and slaves are in different clock domain, we need to bring both in the single clock to satisfies this criteria.

 

[ivb1991]

Hi ivb1991,

As per the AMBA® AXI Protocol v1.0 Specification

11.1.1 Clock
Each AXI component uses [B][COLOR="#FF0000"]a single[/COLOR][/B] clock signal, ACLK. All input signals are sampled
on the rising edge of ACLK. All output signal changes must occur after the rising edge
of ACLK.

So in the AXI system (AXI Masters, AXI Slaves and the AXI Bridge) uses the single clock, ACLK for the transaction.

inside the AXI master and/or AXI slaves, there can be multiple clock domains, but the AXI transaction should use the single clock ACLK

I think "single" in this case means "not differential". Docs are written by humans, and could contain mistakes and ambiguities. As I said, on which clocks will operate master and slave depends on designer.

 

[imbichie]

Hi ivb1991,

example of async AXI bridge from ARM(pdf download is available): http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dto0023b/index.html

Thanks for this information about the asynchronous AXI bridge, I was unaware about this

 

[sun_ray]

sun_ray, example of async AXI bridge from ARM(pdf download is available): http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dto0023b/index.html

How to download the corresponding RTL? The document could be downloaded.

How to connect the different pins of the asynchronous FIFO for read address channel? How to connect the different pins of the another asynchronous FIFO to be put between the write data channel?

Regards

- - - Updated - - -

I think "single" in this case means "not differential". Docs are written by humans, and could contain mistakes and ambiguities. As I said, on which clocks will operate master and slave depends on designer.

ivb1991

Can the master and slave clocks be different for AXI 3 also?

 

[ivb1991]

How to download the corresponding RTL? The document could be downloaded.

I don't think that this RTL is free)) You can buy it(crypted) or write yourself, or try to search in web)

Can the master and slave clocks be different for AXI 3 also?

Yes. As I already said(twice by the way), master and slave clocks are defined by you, not the protocol version))