spartan 3 enter boundary scan
A simple IDCODE loop create problem. It pass something like 10 to 50 loops and then cry that the IDCODE mismatch. This is when the FPGA is running.
If I hold the PROG mode, the RESET button (when it's connected to internal GSR), or when the flash doesn't contain valid bitfile (i.e. when the FPGA start-up but doesn't run due to missing bitfile), then there's no problem. I can IOCODE loop 10000 times without problem. Same with programming.
I should try to program without verify, a few times, and after each time, verify. If the verify fail when the FPGA is already running, but give success when I hold PROG button, then it's probably a problem past the flash chip, in the JTAG chain.
However, this make any in-service boundary scan (dubbuging) impractical, if I have to hold PROG or RESET.
I don't have a scope. If I had one, I could verify where the signals get weak along the chain, and correct the problem.
Thanks