1) In what cases the clock gating should be done manually? I know BackEnd tools insert the clock gating on the outputs of the PLLs. Are there more cases where the gated clock should be inserted manually?
2) It's clear that gating a single flop doesn't have a sense. So, what's minimum flop numbers should be used for the clock gating with the shared enable? E.g. will have the sense to gate the clock of 5 flops? 10 flops? 20 flops? How to choose this threshold?
3) So, as for the clock gating, the following setup should be done:
- selection the gating cell
- selection a min number of flops to be gated
What else? How should I define the above parameters? what are commands (e.g. for Synopsys DC)